A Low Power 10-Bit SAR ADC with DT-MOS at Ultra-Low Supply Voltage

  • 簡 豪廷

Student thesis: Master's Thesis

Abstract

With the advancement of fabrication process portable devices and wireless sensor networks are getting more popular Energy-ef?cient design for these devices is necessary to prolong their lifetimes In sensing systems the ADC is one of the key building blocks which requires moderate resolution (8-12 bits) and low sampling rate (100-1000 kS/s) Among various architectures an ultra-low voltage successive-approximation-register (SAR) ADC has better energy efficiency and is suitable for these sensor systems However ultra-low voltage design induces some challenges we need to overcome such as leakage current limitation of bandwidth and noise degradation which result in worse performance of an ADC In this thesis we propose a high-linearity high-bandwidth and low-leakage S/H circuit with the DT-MOS technique which directly mitigates the above-mentioned problems of the S/H circuit and enhances the overall performance of the ADC at ultra-low voltage In addition an asynchronous timing scheme with the combination of DT-MOS and variable resetting timing control is implemented to optimize the operating speed of the SAR ADC and reduce the effect of leakage current The proof-of-concept prototype was fabricated in TSMC 40-nm CMOS technology and the core area occupies 0 0152 mm2 At 0 3 V supply voltage and 100-kS/s it consumes 166 7 nW and achieves 9 03 bits with Nyquist input At 0 4 V supply voltage and 1-MS/s it consumes 796 4 nW and achieves 9 04 bits with Nyquist input The figure-of-merit (FoM) is 3 19 fJ/conversion-step and 1 51 fJ/conversion-step respectively
Date of Award2018 Sep 7
Original languageEnglish
SupervisorSoon-Jyh Chang (Supervisor)

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