A Low Power and High Resolution Pipelined SAR ADC with Loading-Free Architecture

Abstract

This thesis presents a 12-bit 80-MS/s low power pipelined successive approximation register (SAR) analog-to-digital converter (ADC) with loading-free architecture The basic idea of this work is manipulating the capacitor array of the second-stage SAR ADC to serve as the feedback capacitor of the first stage amplifier during its amplification mode In addition to the saving in the occupied area of the total capacitor such an arrangement reduces the power consumption of the used high performance operation amplifier as well resulting in a low-power and compact ADC Additionally the fixed-window function technique is adopted to cut the power consumption and tolerate non-idealities in the first-stage SAR ADC including the comparator’s erroneous judgments incurred by incomplete settling behavior during the capacitor array switching large INL/DNL errors due to the capacitor mismatch and missing codes induced by comparator offset Moreover the direct switching technique is also utilized to reduce the critical path delay between the digital control logic and switching buffers This proof-of-concept ADC is fabricated in TSMC standard low-power 90-nm 1P9M CMOS process with the active area of only 0 117 mm2 The measured peak SNDR is 55 98 dB and effective resolution bandwidth (ERBW) is 35 MHz The total power consumption is 2 72 mW

Date of Award	2014 May 19
Original language	English
Supervisor	Soon-Jyh Chang (Supervisor)