A Real-time Stereo Matching Algorithm with Iterative Aggregation and Its VLSI Implementation

Abstract

Traditional local stereo matching methods which require a window and its weights between the center pixel and neighboring pixels to compute matching cost acquire more computation and consume more resources Once they are implemented in hardware the window-based aggregation decreases the efficiency In this thesis a fast local stereo matching algorithm is proposed by replacing window-based aggregation with three one-dimensional iterative aggregation processes to construct the effective support region The iterative aggregation reduces complexity and is suitable for hardware realization The proposed algorithm computes raw matching costs with Hamming distances of bit-streams resulted from color census transform then uses modified adaptive support weights to perform iterative aggregations for estimation of best disparities Refinement is used to repair error disparities in boundary and occluded regions Furthermore the corresponding VLSI is provided and realized in Altera FPGA The design requires 27k logic elements 78k registers and 4 8Mb RAM and the speed achieves 60 frames per second with 1920 × 1080 resolution and 64 disparity levels in 160 MHz

Date of Award	2015 Aug 12
Original language	English
Supervisor	Jar-Ferr Yang (Supervisor)