A Study of SIMT/MIMD Dual-Mode Multi-Core Processor System Architecture

  • 陳 冠仲

Student thesis: Doctoral Thesis


SIMT machine emerges as a primary computing device in high performance computing since the SIMT execution paradigm can exploit data-level parallelism effectively This dissertation explores the SIMT execution potential on homogeneous multi-core processors which generally run in MIMD mode when utilizing the multi-core resources We address three architecture issues in enabling SIMT execution model on multi-core processor including multithreading execution model kernel thread context placement and thread divergence For the SIMT execution model we propose a fine-grained multithreading mechanism on an ARM-based multi-core system Each of the processor cores stores the kernel thread contexts in its L1 data cache for per-cycle thread-switching requirement For divergence-intensive kernels an Inner Conditional Statement First (ICS-First) mechanism helps early re-convergence to occur and significantly improves the performance The experiment results show that effectiveness in data-parallel processing reduces on average 36% dynamic instructions and boosts the SIMT executions to achieve on average 1 52x and up to 5x speedups over the MIMD counterpart for OpenCL benchmarks for single issue in-order processor cores By using the explicit vectorization optimization on the kernels the SIMT model gains further benefits from the SIMD extension and achieves 1 71x speedup over the MIMD approach The SIMT model using in-order superscalar processor cores outperforms the MIMD model that uses superscalar out-of-order processor cores by 40 percent This study shows that to exploit data-level parallelism enabling the SIMT model on homogeneous multi-core processors is important
Date of Award2018 Feb 7
Original languageEnglish
SupervisorChung-Ho Chen (Supervisor)

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