An 11-bit 20MS/s SAR ADC Using a Low-complexity Code-dependent Reference Ripple Suppression Technique

  • 吳 皓昇

Student thesis: Doctoral Thesis

Abstract

A single-channel 11-bit 20-MS/s successive-approximation register (SAR) analog-to-digital converter (ADC) with an on-chip reference buffer and the proposed low-complexity code-dependent reference ripple suppression (LCRRS) technique is presented in this thesis The proposed technique is able to suppress all code-dependent reference perturbations in a SAR ADC using commonly-used switching procedures Compared with similar techniques the complexity of the proposed compensation hardware increases linearly instead of increasing exponentially with respect to the number of switching step which suppresses the effect of trumpet-shaped feature in differential nonlinearity (DNL) and enables further power savings on the reference generator with little extra hardware The proof-of-concept prototype was fabricated in TSMC 180-nm CMOS technology The core area occupies 0 563 mm2 At 1 8 V sampling rate of 20 MS/s and Nyquist input the effective number of bits (ENOB) is 10 33 bits and the total power consumption is 3 132 mW with the proposed technique which results in a figure-of-merit (FoM) of 121 7 fJ/conversion-step DNL and integral nonlinearity (INL) with the proposed technique are 0 74/-0 70 LSB and 0 67/-0 73 LSB respectively compared to DNL of 4 06/-1 00 LSB and INL of 4 19/-3 80 LSB without the proposed technique The measurement results also show that the proposed technique renders the static performance less sensitive to the power consumption of the reference buffer
Date of Award2019
Original languageEnglish
SupervisorSoon-Jyh Chang (Supervisor)

Cite this

'