An 8-bit 100-MHz SAR ADC-Based Mixed-Signal Accelerator for Neural Networks

Abstract

This thesis presents an 8-bit 100-MHz SAR ADC-based mixed-signal accelerator for neural networks In addition to quantizing the activations and weights in neural networks the analog computation is adopted in the accelerator to further reduce the energy consumption per arithmetic operation Moreover in order to enhance the top-1 accuracies of neural networks a 5-phase switching scheme which performs the multiply-accumulate (MAC) operation is proposed to mitigate the dynamic offset Last but not least a successive-approximation register (SAR) analog-to-digital converter (ADC) is incorporated into the proposed accelerator to quantize the analog multiply-accumulate signal into the digital output code The proof-of-concept prototype was fabricated in TSMC 40-nm CMOS standard 1P9M process where the chip occupies 2 613 mm2 and the core circuit accounts for 25 8% of the total area With 100-MHz clock frequency and 0 9-V supply voltage the design achieves the top-1 accuracies of 99 3% and 87 3% on MNIST and CIFAR10 datasets respectively In addition the energy efficiency of 3 3TOPS/W is attained and the figure of merit (FOM) i e the energy consumption per arithmetic operation normalized to the quantization steps of the ADC output is 1 18 fJ/step To achieve better energy efficiency and FOM the prototype is operated with 80-MHz clock frequency and 0 7-V supply voltage In this case the top-1 accuracies on MNIST and CIFAR10 datasets are 99 3% and 86% respectively The energy efficiency and FOM are 6 34 TOPS/W and 0 62fJ/step respectively

Date of Award	2020
Original language	English
Supervisor	Soon-Jyh Chang (Supervisor)