An 8-bit 400-MS/s Calibration-Free SAR ADC with a Pre-amplifier-only Comparator

Abstract

A single-channel 8-bit 400-MS/s successive-approximation register (SAR) analog-to-digital converter (ADC) in 90-nm CMOS process is presented in this thesis We propose a hybrid architecture for high-speed SAR ADC without a complex calibration engine The operation speed is enhanced by adopting the loop-unrolled technique in the coarse conversions Considering the mismatch between coarse and fine conversions we adopt the non-binary search scheme with redundancy to maintain the overall performance Moreover two circuit techniques are proposed to increase the operation speed in the fine conversions Firstly a pre-amplifier-only comparator is proposed to shorten the critical timing path in the fine conversions It significantly reduces the comparator reset time Secondly we propose a high-gain dynamic pre-amplifier to mitigate the offset mismatches among the latches for the requirement of the overall accuracy With the above-mentioned techniques it leads to a calibration-free design The proof-of-concept prototype was fabricated in a TSMC 90-nm CMOS technology The core area occupies 0 0276 mm2 At a supply voltage of 1 2-V and sampling rate of 400-MS/s the power consumption of the SAR ADC is 3 198 mW The peak ENOB is 7 15 bits without complex calibration circuit It achieves a figure of merit (FoM) of 56 29 fJ/conversion-step

Date of Award	2016 Nov 15
Original language	English
Supervisor	Soon-Jyh Chang (Supervisor)