An Edge-enhanced Super Resolution Algorithm and Its FPGA implementations

  • 許 芸寧

Student thesis: Master's Thesis

Abstract

In this thesis an edge-enhanced super resolution algorithm is proposed The algorithm consists of two major parts edge-enhanced interpolation and high frequency enhancement The interpolation method can be further separated into two steps In the first step the unknown pixels in the diagonal direction are first classified into with and without edge which will deal with an early skipped interpolation and a strict interpolation method respectively In the second step horizontal or vertical interpolation method is adopted to fill up the reminding pixels in horizontal or vertical direction After interpolations a high frequency enhancement method with a degradation function is finally applied to avoid the aliasing effect and enhancing the high frequency region Moreover a hardware architecture is designed for the proposed algorithm to reduce execution time Experimental results shows that the proposed algorithm achieves 28 448 dB in the average PSNR and 0 8740 in the average SSIM Besides the VLSI architecture can achieve 216 MHz with 6 2 k logic elements on Altera FPGA
Date of Award2015 Aug 12
Original languageEnglish
SupervisorBin-Da Liu (Supervisor)

Cite this

An Edge-enhanced Super Resolution Algorithm and Its FPGA implementations
芸寧, 許. (Author). 2015 Aug 12

Student thesis: Master's Thesis