An Effective On-Line Self-Testing Methodology for an OS-Managed Processor Core and Cache Platform

Abstract

Software-based self-test (SBST) is an effective method to detect operational faults of a processor system We propose an architectural approach to support high fault-coverage on-line SBST: Processor Shield which tackles the difficult-to-test issues raised due to the protection of an operating system The processor shield including a software framework and design for testing (DFT) hardware creates an on-line self-testing environment without influencing other processes and on-bus devices even if the SBST fails We present a case study that demonstrates SBST executions under Linux kernel on an ARMv5-compatible processor system For CPU testing the stuck-at fault coverage is over 99% while the transition fault coverage is higher than 93% For cache control logic testing the stuck-at fault coverage is over 99% while the transition fault coverage is higher than 95% For RAM module testing the fault coverage is nearly 100% Cache SBSTs finish in a context-switch interval of less than 4ms while CPU SBST finishes in less than 8ms for 1 GHz clock The hardware overhead of the processor shield is only 0 494% of the whole processor area We also present an SBST-DVFS application that calibrates the dynamic minimal guardbands and helps achieving lower power consumption and mitigating transistor-aging effect

Date of Award	2017 Aug 18
Original language	English
Supervisor	Chung-Ho Chen (Supervisor)