An Improved Stride-based Encoding Scheme for Packet Classification with Update

Abstract

Packet classification plays a very important role in today's network architecture and that can support many services such as firewall Quality of Service (QoS) traffic control virtual private network (VPNs) etc But in recent years with the rapid development of the Internet and the emergence of software-defined networking (SDN) the methods used for the traditional 5-dimensional packet classification must be extended to support the current rule set which is 12-dimension or 15-dimension Therefore how to simultaneously support more dimensions and support large rule sets and still achieve high throughput is the major issue of current design To achieve high performance the existing methods are implementations on hardware FPGA Although these methods contain a high performance they are often unable to accommodate the larger set of rules because of the restriction of on-chip memory on FPGA In this thesis by observing the existing methods [11] we can find that when using the memory of Xilinx Virtex-Series FPGA the memory may be configured more than we need because of the affected memory characteristics FPGA itself These wasted space will affect the number of rules that can be supported Therefore we will propose a grouping method and update architecture based on stride-based method with Bit-Vector to solve the problem And the consequent benefit is the amount of other resources that will also be reduced Based on our implementation result on Xilinx Virtex-7 XC7V2000T we can support more than 5K 12-dimension rules By using the pipelined and parallel architecture the sustained clock rate is more than 366 MHz and our approach uses less memory (bytes / rule) and can support more number of rules than the existing methods

Date of Award	2015 Aug 25
Original language	English
Supervisor	Yeim-Kuan Chang (Supervisor)