Analysis of the Multi-Vt FD-SOI MOSFETs and SRAM Application

  • 陳 政邑

Student thesis: Master's Thesis

Abstract

As CMOS technology industry continues to scale especially at sub 22 nm node many physical limitations mostly related to short channel effect (SCE) such as drain-induced barrier lowering and hot carrier effect have surfaced The mainstream solution is to use 3D structure devices e g FinFET and Gate-All-Around (GAA) FET to increase the gate controllability However we can still use FD-SOI of the 2D planar structure to eliminate SCE because of its excellent electrostatic control of channel with no channel doping required Compared to FinFET a simpler process is used in FD-SOI and we can control its threshold voltage by modifying back bias or changing substrate doping This thesis demonstrates a body-biasing 6T-SRAM design technique using 5nm-node mutil-Vt FD-SOI devices which offers three operation modes: high-performance mode standard mode and low-voltage mode without complicated process technology requirements The read SNM and write current are demonstrated using Synopsys Sentaurus TCAD mixed-mode simulation We also make use of the technique to optimize Vmin of the 6T-SRAM based on 5nm-node multi-Vt FD-SOI devices By properly selecting the back bias the lowest Vmin is achieved for each of the three operation modes: high-performance standard and low-voltage modes The proposed technique offers a design flexibility for optimizing the SRAM performance and yield by adjusting the back bias without complicated process technology requirements
Date of Award2018 Jan 16
Original languageEnglish
SupervisorMeng-Hsueh Chiang (Supervisor)

Cite this

Analysis of the Multi-Vt FD-SOI MOSFETs and SRAM Application
政邑, 陳. (Author). 2018 Jan 16

Student thesis: Master's Thesis