Analysis on Reliability for FinFET with Different Processes

Abstract

In this thesis we investigated devices is advanced-FinFETs and analysis on different high K oxide preheat time and different epitaxy proximity for basic electrical characteristics N-type device hot carrier reliability and p-type device negative bias temperature instability(NBTI) In our study we have three devices with different high K oxide preheat time and three devices with different epitaxy proximity respectively First we explained the motivation of this study and introduced the structure of FinFETs its advantage and disadvantage and it’s field of application Moreover hot carrier effect and NBTI physical mechanism were be introduced Then we introduced the measurement method and the setting of bias condition in this thesis and explained the basis for reliability assessment and its voltage setting We will present the measurement results for ID-VG ID-VD and IG-VG in terms of the basic electrical characteristics of the FinFETs The measurement results show that the different oxide preheat time has no significant effect on the basic electrical properties of the device In the reliability of the N-type hot carrier the degradation of the device is affected by both the interface trap and the oxide layer defect In the P-type negative bias temperature instability the oxide layer defect dominates the degradation There is no significant difference between the electrical degradation trend and magnitude of different high K oxide preheat time The physical mechanism of degradation defect location and gate quality will not be affected by the preheat time Therefore we speculate that the length of preheat time will not affect the electrical characteristics and reliability of devices as long as they have the effect of preheating can be achieved The second part analyzed the different epitaxy proximity The results of the measurements show that there is no significant difference in the basic electrical properties of the devices In the reliability of the N-type hot carrier the degradation of the device is affected by both the interface trap and the oxide layer defect In the P-type negative bias temperature instability the oxide layer defect dominates the degradation There is no obvious difference between the electrical degradation trend and magnitude of different epitaxy proximity and the physical mechanism and defect location will not be influenced by the epitaxy proximity Therefore we speculate that the difference of epitaxy proximity at different positions on the wafer is too small roughly only Angstrom (?) level so it will not affect the electrical and reliability of the devices

Date of Award	2018 Jul 5
Original language	English
Supervisor	Jone-Fang Chen (Supervisor)