Critical Process Development in Power AlGaN/GaN MIS-HEMTs and p-GaN HEMTs

Abstract

In this thesis we described in details process development for MIS-HEMT focusing on the discussion of Au-free ohmic contact Transmission line measurement (TLM) structure was adopted heavily to step analysis including device isolation using implantation digital etching concept to avoid instability unevenness roughness caused by traditional etching etching profile recovery Au-free ohmic contact and P-GaN active test We have analyzed device characteristics including I-V C-V breakdown voltage and reliability And we discuss P-GaN HEMT as well We have improved the roughness caused by traditional etching from 2 32 to 1 03 nm using digital etching where the stable etching is well-controlled at a rate of 0 93 nm/cycle In the same etching depth the etching depth difference using digital etching is below 10 nm better than the traditional etching is 20 nm For yield and reliability development in digital etching is apparently important Our fabricated device shows the maximum drain current ID(max)=133mA/mm and on-off ratio ION/IOFF=104 at drain bias VD=5V The voltage of the dielectric layer breakdown and device breakdown can achieve 10 V and 422 V respectively After 2000 sec off-state stress on-resistance ratio and threshold voltage shift are 3 and 0 58 V respectively After 1000 sec gate stress with VG=6V threshold voltage shifts 0 7 V In the last part of the thesis the P-GaN gate HEMT has been fabricated successfully but depletion-mode (D-mode) property is observed which is due to Si3N4 deposited by PECVD This reason has been verified by change passivation that gets enhancement-mode (E-mode)

Date of Award	2019
Original language	English
Supervisor	Kuo-Hsing Kao (Supervisor)