Depth Image-Based Rendering and Its VLSI Implementation for New Video and Depth De-packing

  • 林 安傑

Student thesis: Master's Thesis


In this thesis a hardware architecture of depth image-based rendering (DIBR) for new video and depth de-packing is proposed Unlike the format of one view plus one depth the advanced 2D compatible format reduces the bitrates of both color and depth frames In the proposed architecture the Lancos filter is adopted for the proposed two-stage resizing For hardware implementation the coefficients of lanczos filter are modified to the coefficients which can be achieved by shifting For every three pixels in vertical direction total twelve line buffers are used to store the information and output four pixels Then the DIBR system can synthesize the other viewpoints for the 3D display Simulation result shows that the proposed system requires 6 34k gates The proposed architecture can achieve 100 MHz The maximum frame size achieves FHD (1920 × 1088) The proposed architecture achieves 41 dB in the average PSNR
Date of Award2014 Sep 3
Original languageEnglish
SupervisorBin-Da Liu (Supervisor)

Cite this