Design of a Saving-Write-Energy Non-Volatile SRAM

  • 鄒 亦淞

Student thesis: Master's Thesis


With the advancement of technology scaling the leakage current issue becomes one of the most important challenges for SRAMs Existing approaches usually use power gating or low supply voltage well-known data retention voltage to reduce the leakage energy consumption in standby mode With the advent of nvSRAM leakage current can be fully eliminated Compared with conventional approaches it can reach further energy saving by using powering off its supply voltage when data-backup is performed However not all of data are needed to back up In this thesis we propose a novel 10T2R RRAM-based nvSRAM with redundant bit-writes-aware controller which is considering redundant bit-writes condition If data stored in SRAM cells are the same as that in RRAM devices backup can be skipped Otherwise backup is performed As a result backup energy for the data can be saved under redundant bit-writes conditions Simulation shows that energy saving can reach by up to 93% when high resistive state is larger than 10MΩ And as long as the probability of the redundant bit-writes is larger than 25% probability the backup energy saving is achieved The technique can be applied to normally-off computing systems energy harvesting systems L2/L3 Cache and so on
Date of Award2014 Sept 11
Original languageEnglish
SupervisorLih-Yih Chiou (Supervisor)

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