In this thesis we investigate the mechanism of hot-carrier-induced degradation and characteristics of the N-type high voltage metal-oxide-semiconductor with different layout parameters The important layout parameters L G and S They correspond to the length of the gate the length of the drift region and the length between drain contact and shallow trench isolation (STI) respectively In this thesis we will first briefly introduce the application of high-voltage devices in the market and the basic mechanism of the device Subsequently we will introduce the device structure and basic electrical characteristics used in this thesis To gain a deeper understanding of the physical mechanism inside the device TCAD will be used for analysis The second part is will observe the influence of the layout parameters at different positions on the characteristics of the device through basic electrical measurement It is expected that the decrease of L or G enhances IDlin and IDsat especially shortening L increases IDsat the most On the other hand shortening G increases IDlin the most The third part is the effect of gate voltage on hot-carrier degradation The results show that there is a greater degradation at low gate voltage As Nit increases the potential distribution near the bottom of the spacer changes redistributing the electric field resulting in less impact ionization and saturating degradation According to the results it shows that the dominant degradation of the device is the hot-carrier induced Nit generation under the spacer It is speculated that both hot carriers should participate in the degradation of the device The main difference is the ratio of the two carriers At the low gate voltage the contribution of hot holes to the degradation is greater When the gate voltage exceeds 5 75V the contribution of hot electrons to the degradation will gradually increase Besides not only the magnitude of the peak impact ionization rate but also the magnitude of the vertical electric field should be considered when evaluating the hot-carrier induced degradation in this study The fourth part is the effect of layout parameters on the hot-carrier lifetime and breakdown voltage mechanism of the device The scaling parameters L and G will greatly affect the characteristics and reliability of the device However the scaling parameter S affects the breakdown voltage but has little effect on the current and hot carrier lifetime
Date of Award | 2020 |
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Original language | English |
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Supervisor | Jone-Fang Chen (Supervisor) |
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Effects of Device Size on Characteristics and Reliability in High Voltage MOSFET
志邦, 盧. (Author). 2020
Student thesis: Doctoral Thesis