Efficient Memory Management Schemes for Memory-Based FFT Processor Design

  • 羅 信富

Student thesis: Doctoral Thesis


With higher bandwidth efficiency and better immunity to multipath interference orthogonal frequency-division multiplexing (OFDM) technology has been widely adopted in many wireless communication systems For OFDM systems a fast Fourier transform (FFT) processor is an indispensable key component Due to high computation complexity the FFT design was inspired by various hardware architectures to leverage performance and power consumption The memory-based FFT architecture is a low-area design which has significant advantages especially in large-point applications In memory-based FFT design more than 70% area of the processor is comprised of the memory module so the hardware structure access mechanism and addressing method of the memory are key design considerations This dissertation proposes a data relocation mechanism using a merged-bank memory Merged-bank memory uses lower area and power consumption compared to multi-bank memory processors in terms of the hardware implementation Furthermore we propose an efficient and conflict-free memory addressing method based on single-port memory which can be adopted in the hardware implementation and is also applicable to high-radix FFT applications The experimental results show that the single-port and merged-block memory architecture occupies more than 30% less area as compared to dual-port and multi-block memory architecture For the design considerations of low power consumption and high performance cached-memory architecture and pipelined shared-memory FFT architecture are respectively derived from memory-based FFT architecture design For cached-memory FFT processor designs we proposed a memory addressing algorithm applicable to multi-level cached-memory FFT architecture With this algorithm the memory at each level can be realized using merged-bank memory structure so as to maintain the low-area design feature Based on this scheme an 8192-point cached-memory FFT processor for digital video broadcasting (DVB-T/H) applications is demonstrated which uses 10 1-29 3% less area and 9 6-67 9% less power compared to a comparable multi-bank design Finally this dissertation also explores high performance pipelined-memory FFT processor designs A multi-path delay commutator (MDC) architecture and its corresponding addressing algorithm are developed Using such a scheme the data relocation mechanism can be implemented in a way to further integrate the merged-bank memory in the hardware implementation to reduce overall space requirements In addition we also proposed an MDC architecture that supports radix-3 operation which provides more efficient memory management in related applications
Date of Award2016 Jan 27
Original languageEnglish
SupervisorMing-Der Shieh (Supervisor)

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