Energy-Efficiency Soft-IP Design for Median Filter

  • 陳 育呈

Student thesis: Master's Thesis


Median filter is often used in audio processing or image processing No matter in audio or image processing noise is inevitable due to many factors In order to remove noise median filter plays an important role in many different removing noise filters In this dissertation we propose a low-power architecture of partial-bit-level and one-dimensional median filter In principle distinct audio or image standards need different fixed data window-size and bit-width resulting in a need for the compilation of multiple hardware architecture of median filter which corresponds with different data window-size and bit-width The new Soft-IP proposed in this dissertation can support different data window-size and bit-width simultaneously In other words after setting parameters this median filter architecture is able to correspond to a variety of the combination of data window-size and bit-width The proposed design was implemented by using Verilog HDL and synthesized by Synopsys Design Compiler with TSMC 90nm library The experimental results demonstrated can reduce power consumption and flexibility change different window-size and bit-width of median filter
Date of Award2017 Aug 15
Original languageEnglish
SupervisorPei-Yin Chen (Supervisor)

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