Enhanced Electrical Performance and Reliability of Ti-SZTO Thin-Film Transistors with Hf1-xSixO2 Gate Dielectrics Using Co-sputtering Technique

Abstract

The purpose of this thesis is to incorporate appropriate amounts of silicon (Si) in HfO2 dielectric layer and titanium (Ti) in SiZnSnO (SZTO) channel layer using RF co-sputtering processes In addition post deposition annealing (PDA) was also used to reduce the excessive defects in the thin film and improve interface quality Experimental results that Ti-SZTO thin film transistors (TFTs) with Hf1-xSixO2 dielectrics show superior electrical performance and reliability The contents of this thesis is mainly divided into three major parts including “Preparation of SZTO TFTs with Hf1-xSixO2 dielectric layer with analysis of dielectric material properties and device electrical characteristics ” “Preparation of Ti-SZTO TFTs with Hf0 82Si0 18O2 dielectric layer with analysis of channel material properties and device electrical characteristics ” and “Reliability analysis of Ti-SZTO TFTs with Hf1-xSixO2 dielectric layer ” The first part is aims at the research of “Preparation of SZTO TFTs with Hf1-xSixO2 dielectric layer with analysis of dielectric material properties and device electrical characteristics ” which adjust the Si doping ratio in HfO2 to prepare the Hf1-xSixO2 dielectric layer with co-sputtering processes and combine the SZTO channel layer for fabricating SZTO TFTs with a bottom Hf1-xSixO2 gate dielectric Through the material analysis show that Si-O has high bind dissociation energy (BDE) to repair the oxygen vacancies inside the dielectric and reduce the surface roughness of the film which is expected to reduce the defect trapping charge Most importantly due to dielectric and SZTO channel both has Si elements so that can optimize the mismatch of the interface Furthermore the PDA of the device can promote the crystal quality of the dielectric to effectively suppress leakage current and further improve the gate control of the device The experimental results show that Hf0 82Si0 18O2/SZTO TFT can exhibit the best device electrical characteristics among other types of TFTs after dielectric PDA at 600 °C for 10 min in O2 ambient including a higher on/off current ratio (I_on/I_off) of 9 79×107 lower threshold voltage (V_TH) of 0 32 V lower subthreshold swing (SS) of 98 mV/dec higher field-effect mobility (μ_FE) of 31 6 cm2?V-1?s-1 and lower interface trapped density (D_it) of 1 12×1012 cm-2eV-1 The second part is the research of “Preparation of Ti-SZTO TFTs with Hf0 82Si0 18O2 dielectric layer with analysis of channel material properties and device electrical characteristics ” the purpose is to used the best Hf0 82Si0 18O2 dielectric layer which complete at the first of research and combine the Ti-SZTO channel layer in different Ti content by co-sputtering processes In the research process through doping an appropriate proportion of Ti element and PDA with sufficient thermal energy to reduce the oxygen vacancies and interface defects of the films so that the electronic characteristics of the devices can be further optimized The experimental results show that Hf0 82Si0 18O2/Ti(2 5%)SZTO TFT can exhibit the best device electrical characteristics among other types of TFTs after channel PDA at 200 °C for 10 min in N2 ambient including the highest I_on/I_off of 2 78×108 the lowest V_TH of 0 23 V the lowest SS of 87 mV/dec the highest μ_FE of 36 8 cm2?V-1?s-1 and the lowest D_it of 8 97×1011 cm-2eV-1 The third part is the core of the thesis to further explore the benefits of the incorporation of Si in HfO2 dielectric and Ti in SZTO channel layer with stability analysis In addition employing the optimized process parameters obtained from the experimental studies in the first two parts HfO2/SZTO Hf0 82Si0 18O2/SZTO and Hf0 82Si0 18O2/Ti(2 5%)-SZTO TFTs which are referred to devices A B and C respectively were fabricated and compared The influence of Si incorporation in the HfO2 dielectric layer and Ti in the SZTO channel layer on the reliability of TFTs was investigated Experimental results show that On compared with those of device A device C exhibits a smaller threshold voltage shift (?V_TH) in each stability test after hysteresis effect that ?V_TH decreases from 0 310 V to 0 018 V (~94% reduction) after PGBS 1000 s that ?V_TH decreases from 0 642 V to 0 103 V (~83% reduction) after NGBS 1000s that ?V_TH decreases from -0 601 V to -0 096 V (~84% reduction) after thermal test (378 K) 1000 s that ?V_TH decreases from -0 419 V to -0 105 V (~75% reduction) and after NBIS that ?V_TH decreases from -0 569 V to -0 165 V (~71% reduction) respectively Mainly attribute to the improvement of dielectric and channel film quality and interface In addition according to gate leakage analysis it suggests that the dominant leakage mechanisms under high and low electric fields could be Fowler–Nordheim tunneling (F-N) and trap-assisted tunneling (TAT) leakage respectively Ti-SZTO TFTs with Hf1-xSixO2 gate dielectric have been successfully fabricated with co-sputtering processes which effectively improving the interface quality leakage current and gate control to enhance the electrical characteristics and stability of devices It is expected that the proposed Ti-SZTO TFTs with Hf1-xSixO2 dielectrics after suitable post annealing which have been demonstrated having improved electric performance would be a very potential candidate for applications of advanced displays

Date of Award	2020
Original language	English
Supervisor	Shui-Jinn Wang (Supervisor)