Fast Algorithms and Their VLSI Implementation for 3D Video Systems

  • 郭 品岑

Student thesis: Doctoral Thesis

Abstract

In recent years the three-dimensional (3D) video system which is in the representation of color texture and depth brings users a more realistic visual experience To enhance the video quality of the three-dimensional video system this dissertation proposed a three-dimensional video system with fast algorithms and hardware design First a 3DVC encoding system is proposed to reduce the computational complexity of three-dimensional high-efficiency video coding (3D-HEVC) by a fast mode decision method In this method the boundary of the depth map is extracted and applied for the unit partition mode detection before the partition for color texture coding Compared with the related researches this algorithm can reduce about 67 49% encoding time Finally in stereo matching computation adaptive support weight with census transform-based algorithm is then proposed to estimate the depth map In the adaptive support weight method a two-stage method is proposed to reduce the computation A rough depth map is rapidly generated in the first stage while an adaptive refinement method for each case is applied in the second stage The computation time is reduced by about 85% In the census transform based algorithm an iterative aggregation process is proposed which reduces complexity and is suitable for hardware realization Furthermore the corresponding VLSI is provided and the speed achieves 60 fps with 1080p resolution For the depth image-based rendering (DIBR) system two inpainting-based algorithms are proposed for nine views rendering and multi-view rendering respectively The nine views rendering DIBR method is implemented on the GPU which can increase the rendering speed For the multi-view rendering a patch-matched hole filling algorithm is proposed where the best patch is searched with adaptive window size in the surrounding region to fill the holes This work can support 1080p video in real-time at maximum operating frequency 160 2 MHz This dissertation also proposed a hardware architecture for a new texture plus depth format-2Dcompatible packing and de-packing format For the architecture the operation frequency can reach 166 56 MHz which can support the maximum frame size up to FHD in real-time
Date of Award2016 Jul 27
Original languageEnglish
SupervisorBin-Da Liu (Supervisor)

Cite this

Fast Algorithms and Their VLSI Implementation for 3D Video Systems
品岑, 郭. (Author). 2016 Jul 27

Student thesis: Doctoral Thesis