Fully Built-In Low-Power Low-Frequency Oscillator

  • 吳 則緯

Student thesis: Doctoral Thesis

Abstract

Low power consumption is important to wireless communication system To reduce the power consumption we can make the system stay in sleep-mode and send a signal to wake it up and back to operation-mode This thesis propose a fully built-in low power consumption and low frequency oscillator which meets the requirements The output frequency of all versions are designed at 1Hz and three of them are tunable frequency The proposed chip is fabricated by TSMC 0 18μm 1P6M mixed-signal standard CMOS process and the chip area is 0 811 mm2 This chip includes four versions of low-frequency oscillator The oscillator consists of three parts: bias circuit charging-discharging circuit and comparison logic circuit Each version’s core area is 0 083mm^2 0 0098mm^2 0 046mm^2 and 0 053mm^2 The off-chip passive components are needless The output frequency of all versions are 1Hz in the post-simulation But the measurement result isn’t good the lowest frequency is stable at around 355Hz under the same conditions
Date of Award2020
Original languageEnglish
SupervisorChia-Ling Wei (Supervisor)

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