Generating Single- and Double-Pattern Tests for Multiple CMOS Fault Models in One ATPG Run

  • 龔 宜成

Student thesis: Master's Thesis


In this thesis a novel test pattern generation method for multiple DC and AC faults is presented The fault models considered include stuck-at faults bridging faults transition faults and transistor stuck-open faults All faults are transformed into stuck-at faults with some constraints in a proposed two-timeframe circuit model such that all considered faults can be represented utilizing the user-defined fault model which is supported by most commercial ATPG tools This makes it possible to generate all required patterns for both DC and AC faults in one ATPG run with no need to modify the ATPG tool A highly compact pattern set can thus be obtained which requires smaller test data volume and shorter test application time Traditional two-vector test schemes such as LOC and LOS are both supported The proposed two-timeframe circuit model is needed only for ATPG tools to generate test patterns Hence no logic is added to the real circuits Experiments on ISCAS’89 IWLS’05 and ITC’99 benchmark circuits show that compared to the most efficient conventional methods on average our method can reduce test pattern counts by 14 02% 12 12% and 12 97% and test application time by 21 54% 15 03% and 16 3% respectively when the LOC test scheme is employed Experimental results based on the LOS test scheme and the N-detect test method also show higher compaction by the proposed method over previous methods
Date of Award2019
Original languageEnglish
SupervisorKuen-Jong Lee (Supervisor)

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