Hardware Implementation of an Image Interpolation Method with Controllable Sharpness

Abstract

　　The technique of image scaling plays an important role in the digital image processing applications in recent years The image data will be shown on different devices during the process of transmission such as sending photograph from a phone to a computer However as different devices provide different screen and resolution image scaling becomes indispensable for the coordinate between different devices 　　In order to achieve higher quality of the image after scaling an improved algorithm is proposed based on the research of Edge-Preserving Convolution Interpolation (EPI) The EPI algorithm derives linear and convolution interpolation according to error theory yet it cannot obtain the higher image quality at some scaling magnifications The equation is improved by using a controllable sharpness coefficient to obtain a higher result in every magnification While applying the coefficient into the equation this algorithm still retains the characteristic of low complexity Due to the rise of environmental consciousness as well as large power consumption of smart devices the circuit architecture is further analyzed and the Clock Gating technique is applied to the core module to reach the goal of low power 　　Experimental results show that the algorithm can effectively enhance the quality of image scaling and is feasible for VLSI implementation with low complexity By using Synopsys Design Compiler and TSMC 0 13"μm" cell library the synthesis results show that the circuit can achieve 300MHz with gate counts of 12 1K and the total power consumption is 3 77mW As comparing to the original EPI the improved method reduces the power consumption by 10~16%

Date of Award	2015 Aug 12
Original language	English
Supervisor	Pei-Yin Chen (Supervisor)