High-Density Gate-All-Around CMOS Design

Abstract

This dissertation presents a device design methodology for the gate-all-around (GAA) MOSFETs with a focus on high-density VLSI application The non-planar GAA MOSFETs relieve the physical device scaling limitations while the technology roadmap is moving towards sub-10 nm regime Since the drive current of the non-planar device can not be arbitrarily set by the channel width as for the conventional planar MOSFETs and instead it is achieved by a multi-fin configuration a new design methodology is needed to ensure area efficiency Relying on the physical insight to the unique gate-to-gate coupling in the GAA structure high-density SRAM design methodology with optimized device structure is proposed using three-dimensional TCAD simulation and a calibrated macro model Another multi-gate structure – FinFET has been involved in mass production since 22 nm technology FinFETs are generally non-planar and are fabricated on SOI wafers Alternatively feasibility of using bulk-Si wafer is being sought for productivity and cost of wafers and more importantly for the compatibility with bulk CMOS technology However the substrate leakage current underneath the channel requires additional isolation oxide and substrate doping for its suppression In this dissertation the thickness of isolation oxide and concentration of substrate doping are investigated and optimized A new device structure – stacked-gate FinFET is also proposed in order to resolve the leakage current issue (from 10-6 A to 10-9A) without additional substrate doping Two types of GAA MOSFETs in inversion and junctionless (JL) modes are discussed A novel 6T-SRAM design with the pass-gate transistors replaced with JL MOSFTEs is provided to improve static noise margin in the same layout area An electrostatic parameter – scale length is utilized for channel dimension design Yield of 6T-SRAM is estimated based on channel length width and threshold voltage variation Random dopant fluctuations (RDFs) gate line-edge roughness (G-LER) and gate work function (WFV) are investigated for threshold voltage variation A rectangular (thin and wide) channel design is suggested for balanced read/write yield and 28% smaller cell layout area than the double square fin design Multi-threshold voltage (Vt) is required for SoC application However how to implement such design spec in stacked GAA MOSFETs which are developed for higher drive current purpose is an issue; conventional gate length adjustment is not sufficient for a wide range of Vt selection We propose a novel stacked technique with in-situ channel doping to achieve multi-threshold voltage for SoC application The benefit and limitation of the proposed technique are investigated An analytical threshold voltage model with effective doping concentration is provided for the design window

Date of Award	2014 Jul 16
Original language	English
Supervisor	Wei-Chou Hsu (Supervisor)