High-Efficiency Test Compression Technology and On-Chip Self-Test Methodology with All Deterministic Compressed Test Patterns Recorded in Low Power Scan Chains

  • 陳 柏任

Student thesis: Master's Thesis

Abstract

This thesis presents a novel test architecture that combines the advantages of high-quality deterministic scan-based test and low-cost built-in self-test The main idea is to record (store) all required compressed test data in a novel scan chain structure and extract and decompress them during testing This requires a very high compression ratio to obtain a low test data volume (TDV) that is smaller than the number of scan cells in the circuit under test To achieve such a high compression ratio we propose a novel compression method that combines broadcast scan as well as a tailored single-input compression architecture We also utilize the concept of scan chain partitioning and clock gating to increase the efficiency of the test flow in our test architecture An on-chip test controller is employed to automatically generate all required control signals for the whole test procedure This significantly reduces the requirements on external ATE Experimental results on the 8-core open-source OpenSPARC T2 processor with 5 7M gates show that all required test data for 100% testable stuck-at fault coverage can be stored in just 59 4% of the scan cells of the processor Though this work is mainly for the testing of stuck-at faults extensions to deal with more fault models fault diagnosis and engineering change orders (ECO) are also discussed
Date of Award2018 Jan 24
Original languageEnglish
SupervisorKuen-Jong Lee (Supervisor)

Cite this

High-Efficiency Test Compression Technology and On-Chip Self-Test Methodology with All Deterministic Compressed Test Patterns Recorded in Low Power Scan Chains
柏任, 陳. (Author). 2018 Jan 24

Student thesis: Master's Thesis