High Step-Down DC-DC Converter with Low Output Voltage Ripple

  • 簡 君?

Student thesis: Master's Thesis


With the advancement of technology people's behavior is stored in the cloud which is becoming a part of information in big data The place where the big data stored has consumed 3 % of the world's electricity consumption every year about 400 terawatts hours which is higher than the electricity consumption of about 300 terawatts hours per year in the United Kingdom Google proposes a new power architecture with 48 V to point-of-load design to reduce the huge consumption from data center After transferring to POL voltage from 48 volt the two stage conversion are required for conventional converter chain but only single stage conversion for new architecture proposed by Google Therefore based on single stage conversion a high step-down DC-DC converter with low output ripple is proposed in this thesis The two coupled inductors are applied to realize the concept of interleave converter and the ripple of output current and output voltage are reduced This converter is suitable for systems with high performance GPUs and CPUs The operating principle and parameter design of the proposed converter are discussed and simulated by the software SIMPLIS? Finally according to the topology proposed in this thesis a circuit with a specification of 48 V input voltage 3 3 V output voltage and 20 A rated current is implemented to verify the feasibility of proposed topology in this thesis
Date of Award2019
Original languageEnglish
SupervisorJiann-Fuh Chen (Supervisor)

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