High-Throughput Turbo Decoder Design with Low-Complexity Interleaver for 3GPP-LTE/LTE-A Systems

Abstract

Turbo codes have been widely adopted by wireless communication standards due to their excellent error correction performance As the next-generation standard 3GPP-LTE/LTE-A systems use turbo coding as the channel coding scheme with a higher throughput demand To meet this higher data rate requirement the highly-parallel turbo decoder architecture is frequently applied How to reduce the complexity of parallel interleaver and increase the throughput rate are essential to the turbo decoder design In this thesis an efficient architecture of turbo decoder is presented by using two-dimension differential calculation interleaver and dummy calculation-reduced parallel-window algorithm to achieve the throughput demand in 3GPP-LTE/LTE-A systems The proposed interleaver can support highly parallel soft-input/soft-output (SISO) decoding architecture with low complexity computation Furthermore the proposed decoding algorithm can increase the throughput rate without performance degradation by reducing the dummy calculation Experimental results show that the developed turbo decoder can improve the normalized area efficiency by about 24 53% compared to related works for high-throughput implementation

Date of Award	2014 Aug 26
Original language	English
Supervisor	Ming-Der Shieh (Supervisor)