Investigation of Device Characteristics and Reliability on High Voltage MOSFET

Abstract

In the thesis hot-carrier-induced degradation and mechanism as well as the gate oxide integrity issue of high voltage metal-oxide–semiconductor field- effect transistors (HVMOS) with different layout parameters were investigated There were three kinds of parameter used in this thesis: Lgs (source-to-gate-edge) Lg (gate-length) and Lgd (drain-to-gate-edge) First the advantages and applications of HVMOS transistors were illustrated Moreover the basic theories of the punch-through breakdown the junction breakdown the gate-induced-drain-leakage (GIDL) and the hot carrier effect were also introduced The measurement setup device and the structure of our study were introduced The measurement results of I-V characteristics including ID-VG & ID-VD was presented In the main part of content the influence of varying the layout parameter on off-state breakdown was studied at first By measurement and Technology on Computer Aided Design (TCAD) it could be observed that there were two different mechanisms dominating the breakdown before and after Lg is varied The Lgs has a small influence on breakdown voltage What’s more shrinking Lgd under a certain limit would not worsen the off-state breakdown voltage After screening out the devices with qualified breakdown voltage the hot carrier reliability of these devices were investigated From the experiment results the hot carrier reliability was deteriorated no matter which dimension parameter shrank Besides the hot carrier degradation mechanism and damaged position were also the same The TCAD simulation indicated that impact ionization rate near Si/SiO2 had small difference in these devices At last according to the experiment results shortening which parameter is the most effective way to increase the performance without affecting the hot carrier reliability too much

Date of Award	2015 Jul 1
Original language	English
Supervisor	Jone-Fang Chen (Supervisor)