Investigation of Trap Properties in Nano Scale High-k/Metal Gate PMOSFETs on 1/f Noise and RTN Characteristics

  • 高 綜絃

Student thesis: Doctoral Thesis


In past several decades the enormous development for complementary metal-oxide-semiconductor (CMOS) technology was based on conventional silicon oxide dielectric and poly-Si gate electrode Due to the downscaling of device dimensions in CMOS technology high-k (HK) materials and metal gate (MG) electrodes have become an important foundation of CMOS technology processes In this thesis HfO2-based gate dielectrics are one of the best choices for replacing SiO2 But the intrinsic defects of HfO2 gate dielectrics have caused serious trapping effects in p-type metal–oxide–semiconductor field-effect transistors (pMOSFETs) and resulted in some reliability and electrically issues On the other hand excessive low-frequency noise which includes 1/f noise and random telegraph noise (RTN) in nanoscale transistors leads to a limitation in the functionality for analog digital mixed-signal and RF circuits In order to improve these problems we have investigated the behaviors of low-frequency drain current noise using the different energies and doses of Al ion implantation (I/I) into HK layer of pMOSFETs devices By utilizing the 1/f noise analysis we can understand the response of traps properties for the different energies and doses of Al I/I pMOSFETs devices of 28-nm technique process For Al I/I in the pMOSFETs this discrepancy should be attributed to the fact that the Al implantation could fill the defects and form a thin Al2O3 layer so that the drive current and effective work function of the pMOSFETs can be effectively improved Through the 1/f noise and RTN analysis as a result the tunneling barrier height φB became larger for holes and the tunneling attenuation length (?) penetrating into the dielectric became shorter However the energies and doses of Al I/I increased the Al implantation also could fill the defects and form a thin Al2O3 layer Higher energies and concentrations of Al have deeply diffused near SiO2/Si interface accompanied with increasing equivalent oxide thickness and caused gate tunneling current density performance degradation due to non-optimized Al implantation Therefore more studies need to carry out to optimize the Al profiles and to minimize the induced worsening of gate leakage by the deep diffusion of Al into the Si substrate Finally we have investigated of low-frequency noise of 28-nm technology process of Al I/I in HK/MG p-MOSFETs with fluorine (F) incorporation The Drain current in devices with F incorporation is significantly higher than the without F incorporation device counterpart The oxide trap density (Nt) with F incorporation devices are significantly lower than the without F incorporation device respectively as a result of λ decreasing In addition by using the RTN the trap depth (XT) of F incorporation devices are located closer to the IL/Si interface maybe result from for F passivating oxygen vacancies and defect sites
Date of Award2016 Jan 7
Original languageEnglish
SupervisorShoou-Jinn Chang (Supervisor)

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