Investigation of Trap Properties of the Insulator in High-k Metal Gate MOSFETs

Abstract

In high-k (HK) generation HfO2-based gate dielectrics which are the best choice for replacing SiO2 cause serious trapping effects in nMOSFETs resulting in some reliability issues Adding ZrO2 can improve the electrical and reliability properties of HfO2-based oxides On the other hand excessive low-frequency noise which includes 1/f noise and random telegraph noise (RTN) in nanoscale transistors leads to a limitation in the functionality for analog digital mixed-signal and RF circuits However previous studies have only reported the device performance C-V hysteresis and reliability properties of devices with ZrO2-added HfO2 dielectric gate stacks This dissertation work investigated trap properties of HfO2 ZrO2 and composited HfxZr1-xO2 gate dielectrics in 28-nm n- and p-MOSFETs by 1/f RTN and C-V hysteresis measurements which can expand fields of past researches For nMOSFETs the mechanism of 1/f noise in device with HfO2 or HfxZr1-xO2 films was described by carrier number fluctuation showing higher oxide trap densities (Nt) Furthermore it was found that the trapping behavior was mainly dominated by the HfO2 film and was dependent on the thickness of the initial HfO2 layer in the ZrO2/HfO2/SiO2 gate-stack Besides reference devices with a pure ZrO2 gate dielectric exhibited 1/f noise characteristics that are consistent with the unified model which incorporates both the carrier number and the correlated mobility fluctuations For pMOSFETs the mechanism of 1/f noise in all tested devices with HfO2 Hf0 83Zr0 17O2 and ZrO2 films was described by the unified model RTN results demonstrated that ZrO2 device had the deepest trap depth (xT) among all devices indicating that ZrO2 HK gate stacks had a deepest effective centroid of the fixed charges As a result the device with ZrO2 exhibited the highest Nt value Fortunately the trapping behavior of hole capture from a ZrO2 film can be suppressed through mixing with a HfO2 film Comparing the trap properties of all tested n- and p-MOSFETs it was found that the trend of C-V hysteresis was consistent with that of Nt value So C-V hysteresis measurement can be a qualitative method for the estimation of trap properties Further the source of the extracted Nt was mainly from border traps which are the traps near the interface of SiO2 interfacial layer and Si substrate From molecular orbital diagrams HfO2 material exhibits more oxygen vacancy defects near conduction band to cause electron trapped easily In contrast ZrO2 material reveals more oxygen interstitial defects near valence band to make hole trapped easily Finally for pMOSFETs with embedded SiGe source/drain the uniaxial compressive strain in the device channel induced the decrease in the tunneling attenuation length reflecting in the oxide trap depth Consequently lower 1/f noise

Date of Award	2015 Jan 20
Original language	English
Supervisor	Jone-Fang Chen (Supervisor)