Low-Latency Warrants Trading System of Risk Management with Speedy FAST Protocol Decoder on NetFPGA

  • 黃 義方

Student thesis: Doctoral Thesis

Abstract

In stock trading low-latency transfers can help investors prioritize the order of transactions in the market Traditionally market transaction data is decoded using software However the task scheduling executed in the operating system leads to high latency so high-frequency trading (High Frequency Trading) technology appears High-frequency trading mainly uses the low-latency features in hardware such as GPU ASIC or FPGA to decode messages so that the processing delay for market data can be maintained at the microsecond level In the automated trading system the time delay of trading message transmission and strategy judgment need to be reduced to achieve the purpose of earning the spread of stock trading The market-making behavior is currently the most widely used high-frequency trading strategy The market-making refers to the continuous limit order on both sides of the order book to provide liquidity and earn the spread For market makers risk control is the most important part To prevent the market making process from causing losses brokers must be ready to delete the buy/sell orders that have been sent according to the immediate market conditions We use the characteristics of high-frequency trading to design a low-latency and fully automatic deletion processing system for the risk management of warrant trading We design and improve the decoding process for the FAST (FIX Adapted for Streaming) Protocol and the Financial Information Exchange Protocol (FIX4 4 version) regulated by the Taiwan stock exchange and using NetFPGA SUME as the implementation platform The system maintains the basic connection of the TCP protocol and the function of transmitting data for the FIX protocol is also implemented The Cuckoo hashing algorithm is implemented on the FPGA platform which realizes the function of storing multiple order information with different prices and quick search for the contents of the order book corresponding to the stock code We use the real-time information on the number of orders to predict the rise and fall of future stock prices to decide when to delete the buy or sell orders in the market Our proposed system decodes the FAST market information packet of the Taiwan Stock Exchange A packet can be completely decoded within an average latency of 31 25(37 5) ns It takes only an average of 469 ns from receiving complete market packet to generating the corresponding FIX order cancel request packets Our system provides market makers with low-latency decoder for the FAST protocol implemented on FPGA can quickly change the trading strategy and make the risk control system more practical and convenient
Date of Award2019
Original languageEnglish
SupervisorYeim-Kuan Chang (Supervisor)

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