On-Chip 3D-IC Test System Design for Pre-bond Post-bond TSV Test and TSV Diagnosis Based on IEEE 1838 Standard

  • 李 良哲

Student thesis: Master's Thesis

Abstract

3D-IC uses the Through Silicon Via (TSV) technology to reduce the connection length between each other circuits and enhance I/O bandwidth It is also suitable to heterogeneous integration for memory logic and analog circuits However due to the stacked structure with many different dies the 3D-IC test flow is more complex than the 2D-IC In the current research on test flow of 3D-IC it can be divided into two main steps Pre-bond and Post-bond test The Post-bond test contains the partial stack TSV and complete stack test A low-cost and high-quality test mechanism is proposed in this thesis We integrate the 3D-IC Test Platform to 3D-IC wrapped with the test interface called IEEE std 1838 and the overall circuits become a 3D-IC Test System The system just needs the external equipment or computer through 1149 1 signals sends the required test vectors and test data to platform and then it will generate all control signals and finish the 3D-IC test flow to achieve Pre-bond and Post-bond test and diagnosis for 3D-IC It can significantly reduce the demand for external test equipment and reduce the test cost of 3D-IC chips by this 3D-IC Test System In order to improve the yield of TSV by N-detection method we further propose an efficient test framework of TSV under the overall test time no increasing; In addition we design a graphical user interface (GUI) to help testers to integrate circuits with 3D-IC Test System quickly and controls the test flow of 3D-IC Test Platform In experimental results we just use 1149 1 signals to send the test data to platform and then the platform can effectively execute test functions that contain bottom die logic circuit test in Pre-bond test logic circuit memory and analog circuit test in Post-bond test as well as TSV test and diagnosis Otherwise the platform can test a single TSV tens to tens of thousands times without increasing test time
Date of Award2014 Jan 27
Original languageEnglish
SupervisorKuen-Jong Lee (Supervisor)

Cite this

On-Chip 3D-IC Test System Design for Pre-bond Post-bond TSV Test and TSV Diagnosis Based on IEEE 1838 Standard
良哲, 李. (Author). 2014 Jan 27

Student thesis: Master's Thesis