Output Bit Selection Methodology for Test Response Compaction

  • 連 唯証

Student thesis: Doctoral Thesis

Abstract

Test response compaction techniques are widely used to reduce test data volume for integrated circuits However the conventional output compaction methods based on Multiple-Input-Signature-Registers (MISR) and/or XOR-tree-based networks often suffer from the problems of error aliasing unknown-values and poor diagnosability In this dissertation we present an alternative technique named the output-bit-selection method for test response compaction By directly observing only a small subset of desired output response bits through some selection logic this method can effectively deal with all the above mentioned problems We first formulate the output-bit-selection problem as a minimum set covering problem and then analyze the efficiency of output-bit-selection method for test response compaction Efficient algorithms that can identify near optimum subsets of output bits to cover all detectable faults in very large circuits are developed The experimental results show that less than 10% of the output response bits of an already very compact test set are enough to achieve 100% single stuck-at fault coverage for most ISCAS benchmark circuits Even better results are obtained for ITC’99 benchmark circuits as less than 3% of output bits are enough to cover all stuck-at faults in these circuits The increase ratio of selected bits to cover other types of faults is shown to be quite small if these faults are taken into account during test generation Furthermore the diagnosis resolution of this method is almost the same as that achieved by observing all output response bits The implementation complexity of the output bit selection method strongly depends on the test architectures employed In this work we investigate how to apply the output-bit- selection method to two general scan architectures: random access scan and serial scan For a circuit with random-access scan scheme very little additional hardware is required for output bit selection as the controller and the row/column decoders in the random-access scan test architecture can be reused to select any desired bits For a serial scan based design we present a counter-based output selection approach that employs a counter and a multiplexer as the selection logic to efficiently select all desired output response bits Two efficient output selection algorithms are presented to determine the desired output responses one using a single counter operation for simpler test control and the other using more counter operations for better test response reduction ratio Experimental results show that for stuck-at faults in large ISCAS’89 and ITC’99 benchmark circuits 48%~90% reduction ratios on test responses can be achieved with only one counter and one multiplexer employed Even better results i e 76%~95% reductions can be obtained for transition faults It is also shown that most diagnosis information can be preserved; in general the diagnosis resolution loss is only 0 00097% on average Since only a counter and a multiplexer are employed for our scheme the required area overhead is quite small ranging between 0 31% and 1 29% In order to further shorten the test application time a multiple-counter-based output selection method is then presented to observe more than one output response bits at each scan-out cycle Experimental results on IWLS’05 benchmark circuits show that compared with the single-counter-based scheme the proposed method can reduce 47%~67% test application time by using 2~4 counters with 1 50%~3 00% area overhead To deal with the unknown-value problems we present an X-Avoidance technique to avoid almost all unknown values during the selection process The remaining small number of unknowns can then be easily dealt with by using very simple masking logic A new bit-selection algorithm with X-Avoidance capability is presented to select appropriate output bits to observe and avoid as many unknown responses as possible Experimental results on IWLS’05 benchmarks show that even when 16% of the responses are unknowns all unknown values can be efficiently avoided while 88%~92% response-volume reduction is achieved The proposed output-bit-selection method has several advantages including very high compaction ratio zero aliasing fully X-tolerance high diagnosability low area overhead and simple test control Also no circuit/ATPG modification is needed hence this method can be easily integrated into any typical industrial test flow to significantly reduce the test cost of both DC- and AC-scan testing with no pattern inflation and no test quality loss
Date of Award2014 Nov 28
Original languageEnglish
SupervisorKuen-Jong Lee (Supervisor)

Cite this

Output Bit Selection Methodology for Test Response Compaction
唯証, 連. (Author). 2014 Nov 28

Student thesis: Doctoral Thesis