Performance Optimization of Gate-All-Around MOSFETs by Inner Spacers at 5 nm Technology Node

  • 陳 仕豪

Student thesis: Master's Thesis

Abstract

The evolution of semiconductor technology has been progressed since Moore’s Law proposed in 1964 Dimension scaling is always the challenge for each technology node to reduce producing cost With the continuous scaling of devices short-channel effects are more and more severe in limiting the performance enhancement Multi-gate struc-tures which enhance the gate control on short-channel effects and optimize the electri-cal characteristics can overcome the limitation; FinFET is generally applied for ad-vanced semiconductor fabrications However for sub-5 nm technology node FinFETs can not offer the enough gate control resulting in worse short-channel effects On the other hand GAA MOSFETs with the superior gate control of channel electrostatic are considered as a possible extension for the following technology nodes Nevertheless they increase the undesirable parasitic capacitances In this thesis an analytical model is used to calculate the parasitic capacitances caused by GAA MOSFETs Next the optimization by inner spacer is presented to re-duce the additional parasitic capacitances Such methodology helps us to ensure that the improvement is effective and feasible Then we use Synopsys TCAD to do the process simulations GAA MOSFETs are processed with SiGe epitaxy Electrical characteristic comparison for the devices with and without inner spacers is discussed 5nm technology node in ITRS roadmap is the specification we adopt in this thesis Different spacer lengths are the main topic; the longer spacers extend the effective channel length and improve short-channel effects Furthermore the future design a new integration scheme featuring bulk Si-base and cost-effective fabrication is proposed To overcome the drawback of GAA MOSFETs compared to FinFET: the increase of parasitic capacitances inner spacers are adopted in fabrication The proposed process is feasible and promising in the future based on our preliminary data
Date of Award2018 Feb 7
LanguageEnglish
SupervisorMeng-Hsueh Chiang (Supervisor)

Cite this

Performance Optimization of Gate-All-Around MOSFETs by Inner Spacers at 5 nm Technology Node
仕豪, 陳. (Author). 2018 Feb 7

Student thesis: Master's Thesis