Range Enhanced Packet Classification Design on FPGA

Abstract

Packet parsing has been a necessary facility at all points in the modern networking infrastructure to support packet classification and security functions Increasing bandwidth and security requirements for high-speed networks rely on advanced hardware packet processing solutions The future of the fast Internet needs powerful routers to support abundant network functionalities such as firewall processing quality of service virtual private networks and other services To provide these services the routers need to classify the packets into different categories based on a set of predefined rules so-called multi-field packet classification Traditional packet classification method that usually considersonly5tuple fields is not sufficient for today's complicated network management requirements OpenFlow switch was born to take care of these complex requirements by using a rule set with rich definition as the software-hardware interface Our proposed scheme called Enhanced Range Lookup (ERL) scheme for packet classification optimize Bit-Vector algorithm in order to support range field matching This paper considers OpenFlow1 0 as our experimental rule sets consisting of 12 tuple header fields[2] To show the performance and compare with other proposed schemes we implement the proposed ERL scheme on multiple version of Field Programmable Gate Array (FPGA) devices Experimental results show that our method can handle 5K OpenFlow rules To our knowledge our proposed scheme is the first range supported method that can sustain the clock rate of more than 380 MHz

Date of Award	2014 Aug 29
Original language	English
Supervisor	Yeim-Kuan Chang (Supervisor)