RAP: Reducing the Energy of Asymmetric Hybrid Last-Level Cache via Repetitive Access Aware Placement and Migration

Abstract

In recent years emerging non-volatile memory (NVM) has favorable properties such as low leakage and high density and has attracted a lot of attention Among them spin-transfer torque magnetoresistive random access memory (STT-MRAM) that has read speed comparable to SRAM is a good candidate to build large last-level caches (LLCs) However STT-MRAM suffers from long write latency and high write energy To mitigate the impact of asymmetric read/write energy and latency hybrid cache designs have been proposed to combine the merits of STT-MRAM and SRAM and good block placement and migration policies are necessary to use the hybrid cache efficiently In this thesis we find that conflict miss occurs on L2 frequently causing the blocks thrash between L2 and LLC If the thrashing block that cause write activities i e dirty thrashing block are placed in STT-MRAM of hybrid LLC these will result in excessive energy consumption especially in memory bound benchmarks Therefore this thesis proposes repetitive access aware placement and migration (RAP) to mitigate energy consumption caused by thrashing block RAP places dirty thrashing blocks into SRAM and migrate clean thrashing blocks which is evicted from SRAM to STT-MRAM RAP can reduce up to 38 04% and 19 96% reduction on average of LLC energy for running four copies of workloads on a four-core system For a four-core system that runs mix workloads our technique also can reduce up to 36 60% and 25 92% on average of LLC energy When compared to the previous access aware policy and adaptive placement and migration policy the proposed technique can reduce 20 20% on average (up to 35 68%) and 9 75 % on average (up to 26 67%) energy consumption with insignificant performance degradation Evaluation results show large energy consumption reduction with minimal performance loss

Date of Award	2017 Nov 20
Original language	English
Supervisor	Ing-Chao Lin (Supervisor)