Routability-driven Powerplanning with Dynamic Voltage Drop Constraint

Abstract

Because a power network has a great impact on the performance of a circuit powerplanning has become a more important stage in a modern VLSI design flow As the semiconductor feature size shrinks and the design complexity increases powerplanning becomes more difficult In order to meet the IR-drop and EM constraints traditional powerplanning often uses excessive power stripes which may lead to routing congestion in signal net routing Moreover they only consider the static power consumption without considering the dynamic power consumption Hence the challenges of modern powerplanning problem include how to minimize routing resources while satisfying the static IR-drop constraint More importantly it has to consider routability while meeting the dynamic IR-drop constraint In this thesis we develop an efficient and effective powerplanning methodology to construct a routability-driven power network for different power profiles which can minimize routing area while satisfying the IR-drop constraint Our methodology consists of the planning stage and post-optimization stage In the planning stage we apply the clustering based algorithm to determine the proper locations of power stripes where the IR-drop and routing congestion are considered at the same time In order to consider dynamic IR-drop constraint the post-optimization stage iteratively constructs a representative voltage violation map according to multiple power profiles and repair IR-drop violations according to the map According to the proposed approach our approach can repair voltage violations efficiently without consuming excessive routing area The experimental results show the proposed methodology achieves promising results in industry designs

Date of Award	2019
Original language	English
Supervisor	Jai-Ming Lin (Supervisor)