Electrostatic discharge (ESD) is an important issue in the reliability of integrated circuits In the CMOS circuit each single device has continuously shrunk due to the development of advanced manufacturing processes but the electrostatic charge in the external environment has not been reduced Even if the size of the ESD device is increased the ESD protection ability will not be proportionally improved As a result the protection of deep sub-micron CMOS integrated circuits against ESD would be reduced Therefore an effective ESD protection circuit has been widely studied There is a core ESD device in the ESD protection circuit and its I-V characteristics within needed operating range are important indicators of ESD protection capabilities Therefore this thesis aims to discuss the I-V characteristics of LDMOS in its different 1 Gate Bias Region 2 Well Depth 3 Width Junction Length and Depth 4 Drift Length and Drift Concentration by using TCAD software The additional high-cost amendments include Gate bias and STI as well as a new structure with 3D LDMOS-LIGBT-SCR Finally we bring the thesis into the Back Gate study within the SOI structure This thesis fully presents the simulation results and summarizes the conclusions and guidelines to design the ESD devices that meet the Safe Design Window Also the simulation results will provide a good reference for future actual design
TCAD Simulation-Based Study on LDMOS and LIGBT Power Devices Application on ESD Discharging
宇森, ?. (Author). 2020
Student thesis: Doctoral Thesis