Test and Diagnosis Methodology for Various Fault Models in Logic Circuits

Abstract

With the shrinking manufacturing process and increasing design complexity the defect behaviors in contemporary integrated circuits have become much more complex than ever It is generally realized that the test set for a simple single fault model such as the stuck-at fault model or transition delay fault model is insufficient to detect all defects Hence it is necessary to use more accurate and often more than one fault model in order to avoid test escapes and increase defect coverage resulting in long test time for whole test and diagnosis flow The low defect coverage also causes that the diagnosis analysis tool cannot identify the fault site and location of real defect efficiently In this dissertation we propose the test and diagnosis methodology to deal with various fault models to reduce the cost problems due to large amount of test and diagnosis data volume We apply our methodology to various fault models including time-dependent fault models time-independent fault models and undefined defects By using a commercial ATPG tool a compact set of test and diagnosis pattern can be generated to detect various fault models and distinguish the fault pair that consists of two faults Not only speeding up the whole test and diagnosis flow but also increasing the efficiency of diagnosis analysis (identify the defect location and defect type) resulting in much lower test and diagnosis cost The generated diagnosis patterns can help us identify the real defect efficiently However due to the limitation of logic circuit there are still many functionally-equivalent faults that cannot be distinguished by any possible test In our dissertation we develop a repair-for-diagnosis architecture to help us distinguish those functionally-equivalent faults Bu adding the redundant transistors or redundant gates into the fault site of those functionally-equivalent faults we can identify the location and type of real defect if repairing is successful We can apply this repair-for-diagnosis architecture to new advance manufacturing process to identify the real defect quickly and improve chip yields efficiently

Date of Award	2018 Jul 31
Original language	English
Supervisor	Kuen-Jong Lee (Supervisor)