The Development of Optimized Source/Drain Structures and Novel Channel/Dielectric Materials for Amorphous IGZO Thin-film Transistors

  • 洪 健雄

Student thesis: Doctoral Thesis

Abstract

Researches on oxide-semiconductor-based thin-film transistors (TFTs) have advanced remarkably in recent years Commercial display products using indium gallium zinc oxide (IGZO) active arrays have also been successfully demonstrated It is highly expected that the oxide semiconductor could have a high potential for using in display and system-on-panel application In order to improve the electrical performance of IGZO TFTs various technologies or schemes have been reported to lower driving-voltage enhance carrier mobility reduce leakage current and improve gate control ability In the present dissertation to further polish the performance of IGZO TFTs the optimized engineering of source/drain (S/D) contact gate dielectrics and channel of IGZO TFT is demonstrated In the part of S/D contact the sputtered ZnO buffer layer (BL) sandwiched between the S/D electrode and the a-IGZO channel is used to decrease the contact resistance of S/D and improve the electrical performance Sequentially in order to decrease the leakage current of IGZO TFT the Schottky contact source would be used to provide a Schottky barrier height for resisting the carrier transport at off-state of device In another aspect we fabricated the ZrSiO gate dielectric and Ti-doped channel to improve the electrical performance and reliability of TFT The best electrical performance of this dissertation is the use of co-sputtered Titanium doped indium gallium zinc oxide (Ti-IGZO) channel with Zr0 85Si0 15O2 gate dielectric It is found that oxygen vacancies in Ti-IGZO channel is decreased after Ti atom incorporation and stability of the TFT could be considerably improved It reveals that Ti-IGZO channel prepared at a power ratio of IGZO:TiO2=80 W:25 W with a PDA a shows the best device performance of I_on?I_off the SS and the ?V_TH after 1000 s positive/negative gate-bias stress are of 1 65×10^8 90 mV/dec and 0 157 V/-0 093 V respectively From the results mentioned above the optimized engineering of source/drain contact and development of novel gate dielectric and channel layer have shown excellent electrical performance In this thesis the RDS can be decreased by insertion of buffer layer and advance the electrical performance To improve the leakage performance of IGZO TFT the IGZO SB-TFT with a Schottky source structure is fabricated and show the lowest leakage current at off-state In addition the novel channel and dielectric layer with low trap density are manufactured by co-sputtering technique As the results IGZO TFTs with the novel channel and dielectric layer show the excellent electrical and reliability performances The S/D optimized engineering and development of novel gate dielectric and channel are very promising for application in system-on-panel (SoP) and organic light-emitting (OLED) display in the future
Date of Award2017 Oct 31
Original languageEnglish
SupervisorShui-Jinn Wang (Supervisor)

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