The Evaluation of 6T-SRAM for GAA MOSFETs and FinFETs at 7 nm and 10 nm Technology Nodes

  • 吳 孟晏

Student thesis: Master's Thesis


As the semiconductor industry continues to advance it has encountered many physical limitations mostly related to short-channel effects (SCEs) Below node 22 the multi-gate structure has become the solution to improve the gate controllability In this thesis we benchmark 6T-SRAM of GAA MOSFETs and FinFETs and present the performance of both devices We find that GAA MOSFETs with stacking technique provide higher drive current (per pitch) than FinFETs do However the intrinsic delay (CV/ID) property is contrary Static random access memory (SRAM) occupies a large portion of die size and consumes most of the standby leakages 6T-SRAM has been designed as different configurations for high density (HD) low voltage (LV) and high performance (HP) Using a calibrated compact model we can project the SNM and writeability of the 6T-SRAM for both devices in different configurations And the characteristics of 6T-SRAM for all combination are demonstrated The yield estimation is also done by the calibrated macro-model The yield estimation and the minimum cell operation voltage (Vmin) for all design combinations of SRAM are presented in this work By adjusting the channel width of the pass-gate devices we optimize the GAA MOSFET SRAM in LV configuration to improve Vmin However this method can not be used for FinFETs Although it suffers from the area penalty the GAA MOSFETs show the potential for SRAM design
Date of Award2016 Jul 18
Original languageEnglish
SupervisorWei-Chou Hsu (Supervisor)

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