The Investigations and 3D Simulations of the Characteristics of Advanced HKMG Bulk FinFETs and SiGe Channels with High Mobility

  • 陳 建宏

Student thesis: Doctoral Thesis


For these years according to ITRS roadmap the size of device keeps scaling It comes to nanodevice’s generation each step of process technology has become more complicated and this is based on more breakthrough of technology If we want to keep scaling based on Moore’s Law technology in addition to the breakthroughs and innovations for traditional process technology the innovation of transistor structure for sub-nano-or even nanoscale transistors is the key-point Bulk FinFET is one of the candidates for device in sub-22 nm technology node because of its good cut-off characteristics short channel effect control and better scalability by double gate mode operation Recent researches on FinFET devices were reported but there are few reports discuss the influence of layout parameter such as fin width fin height and the fin numbers on the electrostatic characteristic of the devices In the first part of this thesis we experimentally fabricate and characterize high-k metal gate (HKMG) bulk FinFET devices and simulate the fin profile with different tapers and rounding The effect of the fin taper and rounding profile on the C-V characterization is assessed by extracting the fabrication parameters accordingly The capacitance-voltage electrical characteristics of fin field-effect transistor (FinFET) varactors which have fins with different taper angles and rounding radiuses are investigated By fitting the results of the three-dimensional correction simulation with those of an experimentally fabricated FinFET varactor two key factors of process simulations (taper angles θ and rounding radius r) are extracted It is found that the the capacitance of the FinFET varactor changes when the fin cross-sectional profile varies The examination presented here is useful in the fabrication of FinFETs It clarifies the fin cross-sectional profile effect on the FinFET varactor capacitance The effects of the depletion capacitance of a varactor between fin field-effect Transistor (FinFET) and bulk planar devices are investigated The depletion capacitance of an NMOS varactor in FinFETs is lower than that of the conventional bulk planar one Thus the NMOS FinFET varactor provides a larger tuning range than the bulk planar one The simulation results of the proposed 3D devices with FinFET and bulk planar varactors show that the depletion layer width of the NMOS varactors in FinFETs is more sensitive to the applied gate voltage than the bulk planar one We for the first time explore the dependence of the silicon fin width on the electrostatic characteristic of HKMG bulk FinFET devices On the same layout area our study indicates that the narrow fin width possesses worse flat band voltage shift and large variation of gate capacitance owing to increased substrate resistance In the second part of this thesis the interface roughness between the Si(1-x)Gex (x=0 25) and SiO2 is experimentally extracted and calculated as a function of root mean square by analysis of high resolution transmission electron microscopy The surface-roughness dependent mobility model is then incorporated into device simulation to study the mobility of SiGe along (110) and (100) orientations of the devices We further analyze four devices with different surface roughness along (100) and (100) orientations to demonstrate the influence of surface roughness on the total effective mobility The Ge concentration play an important role in SiGe channel Fin-FET device A fast more convenient and nondestructive analysis method three-dimensional spectroscopic ellipsometry-optical critical dimension metrology (3D SE-OCD) is used to extract Ge concentrations of SiGe channel FinFETs The refractive index (n) and extinction index (k) of SiGe with different Ge concentrations investigated under wavelengths ln = 370 nm and lk = 525 nm Results show that the Ge concentration of SiGe channel can be accurately measured using a 3D SE-OCD
Date of Award2014 Nov 6
Original languageEnglish
SupervisorSheng-Yuan Chu (Supervisor)

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