The VLSI Design and Implementation for One-Dimensional Median Filter

Abstract

A median filter is a nonlinear filter widely used in digital signal and image processing for filtering out impulse noise while preserving the crucial properties of the underlying signal Many practical real-time image applications typically require the hardware imple-mentation of a median filter This dissertation presents two VLSI architectures for a one-dimensional (1-D) median filter Word-level samples were sequentially processed by word The median of a set of samples is often computed by sorting the samples and then selecting the middle value When a sample enters the window the oldest sample is removed and the new sample is inserted in an appropriate position For the first architecture proposed in this dissertation the concept in [11] was extended by proposing a new word-level 1-D filter architecture For achieving the objective of high-throughput and area-efficient VLSI implementation of the proposed method the processes of deleting and inserting samples were combined into one clock cy-cle (a new control circuit is proposed for governing these two operations) The combina-tional control unit was then implemented using a logic optimization method The proposed design was compared with that of a previous study and the results indicated that the pro-posed design demonstrated superior area efficiency The median of a set of samples in the word-level sorting network is conventionally computed by first sorting the input samples and then selecting the middle value In these conventional methods when a new sample enters the window some of the stored samples must be shifted left or right depending on their values For some applications that require a larger sample width more signal transitions are required in the circuit (i e more dynamic power is consumed) For solving this problem the second architecture proposed in this disser-tation a low power consumption architecture is proposed for designing of a 1D median filter which was implemented by keeping the stored samples in the window immobile by using a token ring Only the rank of each sample must be updated in each new cycle when an input sample enters the window The power consumption is reduced by decreasing the number of signal transitions in the circuit The experimental results indicated that the power con-sumption for median filters in practical use was successfully reduced at the expense of some area overhead The VLSI architectures of the proposed design were implemented by using Verilog HDL and synthesized by SYNOPSYS Design Vision with the TSMC cell library Concern-ing the chip layout Synopsys IC Compiler was adopted for automatic placement and rout-ing (APR) Finally Synopsys Star-RCXT was adopted for parasitic extraction and the total power consumption obtained from the post-layout simulation was measured using Synop-sys PrimeTime PX The synthesis results and total power consumption showed that the proposed designs have the advantages of low cost and low power separately

Date of Award	2015 Jan 30
Original language	English
Supervisor	Pei-Yin Chen (Supervisor)