Timing-Aware Physical Design Methodologies for Implementing Low Power Designs

  • 許 雅婷

Student thesis: Doctoral Thesis


Due to the prevalence of portable electronic products lower power attracts more attention for circuit designs However as technology advances an SOC design can contain more and more components which lead to a higher power density Hence lower power becomes one of the most important issues in modern VLSI designs Reducing power consumption not only can enhance battery life but also can avoid performance degradation induced by the overheating problem There have been many lower power design techniques proposed to reduce system power consumption Among these techniques the multi-bit flip-flop and the power-gated are considered as the most effective approaches Although these two methods both can reduce power consumption they also increase implementation complexity of the physical design For instance we have to replace several single-bit flip-flops by a single multi-bit flip-flop when the multi-bit flip-flop technique is applied to a design But the timing in an original layout may be affected if an improper set of single-bit flip-flops is selected or a new inserted multi-bit flip-flop is placed at improper location This will result in performance degradation or even failure in the functionality Besides when a power-gated technique is applied to a design it may cause severe rush current if the turned-on sequence of power switches or their timing are not properly controlled and thus the reliability of a system is degraded and the response time is increased This dissertation presents two design methodologies which respectively target on implementing multi-bit flip-flops and power-gated techniques in the physical design Since both of two techniques may induce timing-related issues our approaches show the methodologies to resolve these problems and make them feasible in real VLSI designs The experimental results have demonstrated the efficiency and effectiveness of our approaches For the multi-bit flip-flop technique our algorithm can achieve power reduction and simultaneously minimize wirelength without violating timing constraint For the power gated technique the proposed methodology can avoid occurrence of large rush current; hence the reliability of a design is maintained
Date of Award2017 Feb 16
Original languageEnglish
SupervisorSoon-Jyh Chang (Supervisor)

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