TSV-aware Fixed-outline Floorplanning Methodology for 3D ICs

Abstract

A three-dimensional integrated circuit (3D IC) which uses through silicon vias (TSVs) as inter-die connections is one of the promising 3D integration technologies to break through bottlenecks faced by a 2D IC However TSVs are like double-edged swords Despite shorter wirelength brought by TSVs abusing or misplacing TSVs may degrade a 3D IC significantly Moreover a TSV is much larger than a standard cell and will block the placement or routing resources Hence floorplanning in 3D IC should not ignore the existence of TSVs Although many studies have been presented to cope with different problems during 3D floorplanning most of them either neglect the TSV planning or overlook the fixed-outline constraint As a result this thesis proposes a TSV-aware methodology to handle fixed-outline floorplanning for 3D ICs Our approach can obtain better results than others because all modules and TSVs in all tiers of a 3D IC are optimized simultaneously in the global distribution stage Further after better initial solutions are gained our legalization stage still can maintain them and get feasible solutions while considering TSVs under the fixed-outline constraint Experimental results show that our results respectively achieve 10% and 13% shorter wirelength than Co-place in average in benchmarks with hard modules and soft modules

Date of Award	2015 Aug 21
Original language	English
Supervisor	Jai-Ming Lin (Supervisor)