Chung-Ho Chen

查看斯高帕斯 (Scopus) 概要

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每年研究成果

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53 Conference contribution
23 Article
4 Paper
3 Conference article
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- 3 Patent

23結果

篩選

2018
Enabling SIMT execution model on homogeneous multi-Core system
Chen, K. C. & Chen, C. H., 2018 3月, 於: ACM Transactions on Architecture and Code Optimization. 15, 1, a6.
研究成果: Article › 同行評審

開啟存取
3 引文斯高帕斯（Scopus）
2017
A Processor and Cache Online Self-Testing Methodology for OS-Managed Platform
Lin, C. W. & Chen, C. H., 2017 8月, 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25, 8, p. 2346-2359 14 p., 7924426.
研究成果: Article › 同行評審
6 引文斯高帕斯（Scopus）
2014
Virtualization technology for TCP/IP offload engine
Chang, E. H., Wang, C. C., Liu, C. T., Chen, K. C. & Chen, C. H., 2014, 於: IEEE Transactions on Cloud Computing. 2, 2, p. 117-129 13 p., 6245519.
研究成果: Article › 同行評審
7 引文斯高帕斯（Scopus）
2013
A system-level network virtual platform for IPsec processor development
Wang, C. C. & Chen, C. H., 2013 5月, 於: IEICE Transactions on Information and Systems. E96-D, 5, p. 1095-1104 10 p.
研究成果: Article › 同行評審
1 引文斯高帕斯（Scopus）
2011
Effective hybrid test program development for software-based self-testing of pipeline processor cores
Lu, T. H., Chen, C. H. & Lee, K. J., 2011 3月, 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 19, 3, p. 516-520 5 p., 5356222.
研究成果: Article › 同行評審
32 引文斯高帕斯（Scopus）
Energy-efficient Trace Reuse cache for embedded processors
Tsai, Y. Y. & Chen, C. H., 2011 9月, 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 19, 9, p. 1681-1694 14 p., 5545496.
研究成果: Article › 同行評審
11 引文斯高帕斯（Scopus）
2008
Configurable VLSI architecture for deblocking filter in H.264/AVC
Chen, C. M. & Chen, C. H., 2008 8月, 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 16, 8, p. 1072-1082 11 p., 4570475.
研究成果: Article › 同行評審
14 引文斯高帕斯（Scopus）
Frame buffer access reduction for MPEG video decoder
Lin, W. C. & Chen, C. H., 2008 10月, 於: IEEE Transactions on Circuits and Systems for Video Technology. 18, 10, p. 1452-1456 5 p., 4633657.
研究成果: Article › 同行評審
1 引文斯高帕斯（Scopus）
2007
An efficient pipeline architecture for deblocking filter in H.264/AVC
Chen, C. M. & Chen, C. H., 2007 1月, 於: IEICE Transactions on Information and Systems. E90-D, 1, p. 99-107 9 p.
研究成果: Article › 同行評審
10 引文斯高帕斯（Scopus）
Scalable dynamic instruction scheduler through wake-up spatial locality
Chen, C. H. & Hsiao, K. S., 2007 11月, 於: IEEE Transactions on Computers. 56, 11, p. 1534-1548 15 p.
研究成果: Article › 同行評審
4 引文斯高帕斯（Scopus）
Scalable IPv6 lookup/update design for high-throughput routers
Chen, C. H., Hsu, C. H. & Wang, C. C., 2007 7月, 於: Journal of Internet Technology. 8, 3, p. 261-269 9 p.
研究成果: Article › 同行評審
Software-based self-testing with multiple-level abstractions for soft processor cores
Chen, C. H., Wei, C. K., Lu, T. H. & Gao, H. W., 2007 5月, 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 15, 5, p. 505-517 13 p.
研究成果: Article › 同行評審
32 引文斯高帕斯（Scopus）
Window architecture for deblocking filter in H.264/AVC
Chen, C. M. & Chen, C. H., 2007 12月 1, 於: International Journal of Innovative Computing, Information and Control. 3, 6 B, p. 1677-1695 19 p.
研究成果: Article › 同行評審
1 引文斯高帕斯（Scopus）
2006
Wake-up logic optimizations through selective match and wakeup range limitation
Hsiao, K. S. & Chen, C. H., 2006 10月, 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 14, 10, p. 1089-1102 14 p., 1715346.
研究成果: Article › 同行評審
2 引文斯高帕斯（Scopus）
2001
A systematic approach for parallel CRC computations
Shieh, M. D., Sheu, M. H., Chen, C. H. & Lo, H. F., 2001 5月, 於: Journal of Information Science and Engineering. 17, 3, p. 445-461 17 p.
研究成果: Article › 同行評審
39 引文斯高帕斯（Scopus）
2000
Performance evaluation of load/store issue and memory access policies
Chen, C. H. & Wu, A., 2000, 於: Journal of the Chinese Institute of Engineers, Transactions of the Chinese Institute of Engineers,Series A/Chung-kuo Kung Ch'eng Hsuch K'an. 23, 6, p. 697-709 13 p.
研究成果: Article › 同行評審
1999
An easy-to-use approach for practical bus-based system design
Chen, C. H. & Lin, F. F., 1999 8月, 於: IEEE Transactions on Computers. 48, 8, p. 780-793 14 p.
研究成果: Article › 同行評審
4 引文斯高帕斯（Scopus）
Fault-containment in cache memories for TMR redundant processor systems
Chen, C. H. & Somani, A. K., 1999, 於: IEEE Transactions on Computers. 48, 4, p. 386-397 12 p.
研究成果: Article › 同行評審
18 引文斯高帕斯（Scopus）
1998
Exploring the design space of cache memories, bus width, and burst transfer memory systems
Chen, C. H., 1998, 於: Journal of the Chinese Institute of Engineers, Transactions of the Chinese Institute of Engineers,Series A/Chung-kuo Kung Ch'eng Hsuch K'an. 21, 3, p. 269-282 14 p.
研究成果: Article › 同行評審
2 引文斯高帕斯（Scopus）
1996
Architecture technique trade-offs using mean memory delay time
Chen, C. H. & Somani, A. K., 1996, 於: IEEE Transactions on Computers. 45, 10, p. 1089-1100 12 p.
研究成果: Article › 同行評審
3 引文斯高帕斯（Scopus）
Cache write generate for parallel image processing on shared memory architectures
Wittenbrink, C. M., Somani, A. K. & Chen, C. H., 1996, 於: IEEE Transactions on Image Processing. 5, 7, p. 1204-1208 5 p.
研究成果: Article › 同行評審
2 引文斯高帕斯（Scopus）
1995
Proteus: A reconfigurable computational network for computer vision
Haralick, R. M., Somani, A. K., Wittenbrink, C., Johnson, R., Cooper, K., Shapiro, L. G., Phillips, I. T., Hwang, J. N., Cheung, W., Yao, Y. H., Chen, C. H., Yang, L., Daugherty, B., Lorbeski, B., Loving, K., Miller, T., Parkins, L. & Soos, S., 1995 3月, 於: Machine Vision and Applications. 8, 2, p. 85-100 16 p.
研究成果: Article › 同行評審
2 引文斯高帕斯（Scopus）
1990
A performance simulation of local area networks using CSMA/CD and token bus protocols
Stigall, P. D. & Chen, C. H., 1990, 於: Computers and Electrical Engineering. 16, 3, p. 171-175 5 p.
研究成果: Article › 同行評審

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