盧達生

Sung, P. J., Su, C. J., Lu, D. D., Luo, S. X., Kao, K. H., Ciou, J. Y., Jao, C. Y., Hsu, H. S., Wang, C. J., Hong, T. C., Liao, T. H., Fang, C. C., Wang, Y. S., Huang, H. F., Li, J. H., Huang, Y. C., Hsueh, F. K., Wu, C. T., Ma, W. C. Y., Huang, K. P. 及其他6, Lee, Y. J., Chao, T. S., Li, J. Y., Wu, W. F., Yeh, W. K. & Wang, Y. H., 2019 四月, 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019. Institute of Electrical and Electronics Engineers Inc., 8804663. (2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019).

研究成果: Conference contribution

Impact of Semiconductor Permittivity Reduction on Electrical Characteristics of Nanoscale MOSFETs

Chen, S. H., Lian, S. W., Wu, T. R., Chang, T. R., Liou, J. M., Lu, D. D., Kao, K. H., Chen, N. Y., Lee, W. J. & Tsai, J. H., 2019 六月, 於 : IEEE Transactions on Electron Devices. 66, 6, p. 2509-2512 4 p., 8704283.

研究成果: Article

An FET with a Source Tunneling Barrier Showing Suppressed Short-Channel Effects for Low-Power Applications

Hsieh, Y. F., Chen, S. H., Chen, N. Y., Lee, W. J., Tsai, J. H., Chen, C. N., Chiang, M-H., Lu, D. & Kao, K-H., 2018 三月 1, 於 : IEEE Transactions on Electron Devices. 65, 3, p. 855-859 5 p.

研究成果: Article

1 引文斯高帕斯（Scopus）

Emerging NVM circuit techniques and implementations for energy-efficient systems

Khwa, W. S., Lu, D., Dou, C. M. & Chang, M. F., 2018 一月 1, Beyond-CMOS Technologies for Next Generation Computer Design. Springer International Publishing, p. 85-132 48 p.

研究成果: Chapter

1 引文斯高帕斯（Scopus）

FinFET with encased air-gap spacers for high-performance and low-energy circuits

Sachid, A. B., Huang, Y. M., Chen, Y. J., Chen, C. C., Lu, D. D., Chen, M. C. & Hu, C., 2017 一月, 於 : IEEE Electron Device Letters. 38, 1, p. 16-19 4 p., 7744575.

研究成果: Article

17 引文斯高帕斯（Scopus）

論文

金屬-絕緣層-金屬二極體之特性研究

作者: 逸軒, 陳., 2016 八月 12

監督員: Lu, D. (Supervisor)

學生論文: Master's Thesis

盧 達生

學歷

研究專長

經歷

盧達生