• 684 引文
  • 13 h-指數
19982019

Research output per year

如果您對這些純文本內容做了任何改變,很快就會看到。

個人檔案

學歷

  • 2002 國立交通大學資訊科學博士

研究專長

  • 奈米積體電路自動化

經歷

  • 2002~2007 瑞昱半導體研發中心設計自動化部專案副理
  • 2007~2012 國立成功大學電機系助理教授
  • 2012~迄今 國立成功大學電機系副教授

指紋 查看啟用 Jai-Ming Lin 的研究主題。這些主題標籤來自此人的作品。共同形成了獨特的指紋。

  • 4 類似的個人檔案

網路 國家層面的近期外部共同作業。通過按一下圓點深入探索詳細資料。

專案

研究成果

A novel macro placement approach based on simulated evolution algorithm

Lin, J. M., Deng, Y. L., Yang, Y. C., Chen, J. J. & Chen, Y. C., 2019 十一月, 2019 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2019 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 8942168. (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD; 卷 2019-November).

研究成果: Conference contribution

  • Regularity-aware routability-driven macro placement methodology for mixed-size circuits with obstacles

    Lin, J. M., Deng, Y. L., Li, S. T., Yu, B. H., Chang, L. Y. & Peng, T. W., 2019 一月, 於 : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 27, 1, p. 57-68 12 p., 8478776.

    研究成果: Article

  • Routability-driven mixed-size placement prototyping approach considering design hierarchy and indirect connectivity between macros

    Lin, J. M., Li, S. T. & Wang, Y. T., 2019 六月 2, Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019. Institute of Electrical and Electronics Engineers Inc., a119. (Proceedings - Design Automation Conference).

    研究成果: Conference contribution

  • A fast thermal-aware fixed-outline floorplanning methodology based on analytical models

    Lin, J. M., Chen, T. T., Chang, Y. F., Chang, W. Y., Shyu, Y. T., Chang, Y. J. & Lu, J. M., 2018 十一月 5, 2018 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2018 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., a1. (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD).

    研究成果: Conference contribution

  • 2 引文 斯高帕斯(Scopus)

    Co-synthesis of floorplanning and powerplanning in 3D ICs for multiple supply voltage designs

    Lin, J. M., Huang, C. Y. & Yang, J. Y., 2018 四月 19, Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018. Institute of Electrical and Electronics Engineers Inc., p. 1339-1344 6 p. (Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018; 卷 2018-January).

    研究成果: Conference contribution

  • 1 引文 斯高帕斯(Scopus)

    論文

    A Routability-Driven Macro Placer Following Design Hierarchy Based on Simulated Evolution Algorithm

    作者: 有倫, 鄧., 2018 八月 18

    監督員: Lin, J. (Supervisor)

    學生論文: Master's Thesis

    Design Hierarchy-Guided Placement Prototyping Approach Considering Indirect Connectivity Between Macros

    作者: 思庭, 李., 2018 十月 24

    監督員: Lin, J. (Supervisor)

    學生論文: Master's Thesis

    Multiple-Row Height Cell Placement Algorithm Considering Fence-Region Constraint

    作者: 奕文, 王., 2018 十月 24

    監督員: Lin, J. (Supervisor)

    學生論文: Master's Thesis

    Routability-Driven Macro-Aware Powerplanning Methodology Based on Learning Technique

    作者: 志勝, 許., 2018 八月 18

    監督員: Lin, J. (Supervisor)

    學生論文: Master's Thesis

    Thermal-Aware Floorplanning Methodology Considering Application Dependent Power Based on Learning Techniques

    作者: 泰廷, 陳., 2018 七月 26

    監督員: Lin, J. (Supervisor)

    學生論文: Master's Thesis