• 664 引文
  • 13 h-指數
19982019
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研究成果 1998 2019

2019

Regularity-aware routability-driven macro placement methodology for mixed-size circuits with obstacles

Lin, J-M., Deng, Y. L., Li, S. T., Yu, B. H., Chang, L. Y. & Peng, T. W., 2019 一月 1, 於 : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 27, 1, p. 57-68 12 p., 8478776.

研究成果: Article

Macros
Networks (circuits)
Simulated annealing

Routability-driven mixed-size placement prototyping approach considering design hierarchy and indirect connectivity between macros

Lin, J. M., Li, S. T. & Wang, Y. T., 2019 六月 2, Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019. Institute of Electrical and Electronics Engineers Inc., a119. (Proceedings - Design Automation Conference).

研究成果: Conference contribution

Prototyping
Placement
Macros
Connectivity
Clustering
2018

A fast thermal-aware fixed-outline floorplanning methodology based on analytical models

Lin, J-M., Chen, T. T., Chang, Y. F., Chang, W. Y., Shyu, Y. T., Chang, Y. J. & Lu, J. M., 2018 十一月 5, 2018 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2018 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., a1. (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD).

研究成果: Conference contribution

Analytical models
Temperature
Thermal effects
Integrated circuits
Hot Temperature
1 引文 (Scopus)

Co-synthesis of floorplanning and powerplanning in 3D ICs for multiple supply voltage designs

Lin, J-M., Huang, C. Y. & Yang, J. Y., 2018 四月 19, Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018. Institute of Electrical and Electronics Engineers Inc., 卷 2018-January. p. 1339-1344 6 p.

研究成果: Conference contribution

Electric potential
Module
Networks (circuits)
Methodology
Resources
2 引文 (Scopus)

General floorplanning methodology for 3D ICs with an arbitrary bonding style

Lin, J-M. & Huang, C. Y., 2018 四月 19, Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018. Institute of Electrical and Electronics Engineers Inc., 卷 2018-January. p. 1199-1202 4 p.

研究成果: Conference contribution

Bins
Methodology
Benchmark
Module

Macro-aware row-style power delivery network design for better routability

Lin, J. M., Syu, J. S. & Chen, I. R., 2018 十一月 5, 2018 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2018 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., a15. (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD).

研究成果: Conference contribution

Macros
Electromigration
Linear programming
Electric potential
2017
1 引文 (Scopus)

Regularity-aware routability-driven placement prototyping algorithm for hierarchical mixed-size circuits

Lin, J-M., Yu, B. H. & Chang, L. Y., 2017 二月 16, 2017 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017. Institute of Electrical and Electronics Engineers Inc., p. 438-443 6 p. 7858362. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

研究成果: Conference contribution

Macros
Networks (circuits)
Clustering algorithms
3 引文 (Scopus)
Silicon
Simulated annealing
Integrated circuit design
2016
1 引文 (Scopus)
Switches
VLSI circuits
Product design
Linear programming
Electric power utilization
10 引文 (Scopus)

A Systematic Design Methodology of Asynchronous SAR ADCs

Huang, C. P., Lin, J-M., Shyu, Y. T. & Chang, S-J., 2016 五月 1, 於 : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 24, 5, p. 1835-1848 14 p., 7332786.

研究成果: Article

Digital to analog conversion
Specifications
Silicon
Networks (circuits)
3 引文 (Scopus)

A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling

Lu, L. Y., Chang, C. Y., Chen, Z. H., Yeh, B. T., Lu, T. H., Chen, P. Y., Tang, P. H., Lee, K. J., Chiou, L. Y., Chang, S. J., Tsai, C. H., Chen, C. H. & Lin, J. M., 2016 三月 7, 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016. Institute of Electrical and Electronics Engineers Inc., p. 17-18 2 p. 7427980. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; 卷 25-28-January-2016).

研究成果: Conference contribution

Program processors
Microprocessor chips
Temperature
Voltage scaling
Dynamic frequency scaling
6 引文 (Scopus)

SAINT: Handling module folding and alignment in fixed-outline floorplans for 3D ICs

Lin, J. M., Chiu, P. Y. & Chang, Y. F., 2016 十一月 7, 2016 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2016. Institute of Electrical and Electronics Engineers Inc., 2967071. (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD; 卷 07-10-November-2016).

研究成果: Conference contribution

Networks (circuits)
Electric power utilization
Data storage equipment
Three dimensional integrated circuits
2015

FIXED-OUTLINE FLOORPLANNING APPROACH FOR MIXED-SIZE MODULES

貢獻的翻譯標題: FIXED-OUTLINE FLOORPLANNING APPROACH FOR MIXED-SIZE MODULESLin, J-M., 2015 一月 8, 專利號 8966428

研究成果: Patent

Networks (circuits)
Merging
Wire
Hot Temperature
2 引文 (Scopus)
Switches
Planning
Leakage currents
Electric potential
1 引文 (Scopus)

Routability-driven floorplanning algorithm for mixed-size modules with fixed-outline constraint

Lin, J-M., Hu, C. Y. & Chan, K. C., 2015 五月 28, 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015. Institute of Electrical and Electronics Engineers Inc., 7114531. (2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015).

研究成果: Conference contribution

2014
1 引文 (Scopus)

Current density aware power switch placement algorithm for power gating designs

Lin, J. M., Lin, C. C., Syu, Z. W., Tsai, C. C. & Huang, K., 2014 一月 1, ISPD 2014 - Proceedings of the 2014 ACM International Symposium on Physical Design. Association for Computing Machinery, p. 85-92 8 p. (Proceedings of the International Symposium on Physical Design).

研究成果: Conference contribution

Current density
Switches
Leakage currents
Networks (circuits)
Electric potential
8 引文 (Scopus)
VLSI circuits
Electric potential
Thermal effects
Voltage drop

MULTI-POINT TEMPERATURE SENSING METHOD FOR INTEGRATED CIRCUIT CHIP AND SYSTEM OF THE SAME

貢獻的翻譯標題: 適用於積體電路晶片之多點溫度感測方法及其系統Lee, K-J., Chen, C-H., Su, W-Y., Chang, S-J., Chiou, L-Y., Kuo, C-H., Tsai, C-H. & Lin, J-M., 2014 十一月 20, 專利號 9448122

研究成果: Patent

Temperature sensors
Integrated circuits
Temperature
Temperature control
Control systems
2013
4 引文 (Scopus)

A 12-bit 4-kHz incremental ADC with loading-free extended counting technique

Chao, I. J., Huang, C. C., Wu, Y. C., Liu, B-D., Huang, C. Y. & Lin, J-M., 2013 五月 27, p. 29-32. 4 p.

研究成果: Paper

Topology
Operational amplifiers
Clocks
Electric power utilization
Calibration
4 引文 (Scopus)

A flexible fixed-outline floorplanning methodology for mixed-size modules

Chan, K. C., Hsu, C. J. & Lin, J. M., 2013 五月 20, 2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013. p. 435-440 6 p. 6509635. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

研究成果: Conference contribution

Merging
Networks (circuits)
Hot Temperature
37 引文 (Scopus)

Effective and efficient approach for power reduction by using multi-bit flip-flops

Shyu, Y. T., Lin, J. M., Huang, C. P., Lin, C. W., Lin, Y. Z. & Chang, S. J., 2013 一月 1, 於 : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 21, 4, p. 624-635 12 p., 6178020.

研究成果: Article

Flip flop circuits
Integrated circuits
Clocks
Electric power utilization
Networks (circuits)
2012
6 引文 (Scopus)
Error compensation
Capacitors
Capacitance
Analog integrated circuits
Simulated annealing
22 引文 (Scopus)
Capacitors
Analog circuits
Simulated annealing
Signal processing
Electric power utilization
9 引文 (Scopus)

Routability-driven placement algorithm for analog integrated circuits

Lin, C. W., Lu, C. C., Lin, J-M. & Chang, S-J., 2012 五月 1, ISPD'12 - Proceedings of the 2012 International Symposium on Physical Design. p. 71-78 8 p. (Proceedings of the International Symposium on Physical Design).

研究成果: Conference contribution

Placers
Analog circuits
Wire
Analog integrated circuits
25 引文 (Scopus)
Electric potential
Simulated annealing
Planning
7 引文 (Scopus)

Voltage island-driven floorplanning considering level shifter placement

Lin, J. M., Cheng, W. Y., Lee, C. L. & Hsu, R. C. J., 2012 四月 26, ASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference. p. 443-448 6 p. 6164989. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

研究成果: Conference contribution

Planning
Electric potential
Electric power utilization
Wire
2011
27 引文 (Scopus)

Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits

Lin, C. W., Lin, J-M., Chiu, Y. C., Huang, C. P. & Chang, S-J., 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011. p. 528-533 6 p. 5981853

研究成果: Conference contribution

Analog Circuits
Integrated Circuits
Capacitor
Centroid
Placement
5 引文 (Scopus)

Efficient multi-layer obstacle-avoiding preferred direction rectilinear Steiner tree construction

Chuang, J. R. & Lin, J. M., 2011 三月 28, 2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011. p. 527-532 6 p. 5722246. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

研究成果: Conference contribution

Multilayers
Heuristic algorithms
Topology
Intellectual property core
3 引文 (Scopus)

Routing-aware placement algorithms for modern analog integrated circuits

Lin, C. W., Lu, C. C., Huang, C. P., Chang, S-J. & Lin, J-M., 2011, 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011. 6026537

研究成果: Conference contribution

Analog circuits
Capacitors
Automation
Analog integrated circuits
Networks (circuits)
12 引文 (Scopus)
Convex optimization
MATLAB
Cones
Industry
2010
14 引文 (Scopus)

Performance-driven analog placement considering boundary constraint

Lin, C. W., Lin, J. M., Huang, C. P. & Chang, S. J., 2010 九月 7, Proceedings of the 47th Design Automation Conference, DAC '10. p. 292-297 6 p. (Proceedings - Design Automation Conference).

研究成果: Conference contribution

Placement
Wire
Analogue
Symmetry
Module

UFO: Unified convex optimization algorithms for fixed-outline floorplanning

Lin, J. M. & Hung, H., 2010 四月 28, 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010. p. 555-560 6 p. 5419821. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

研究成果: Conference contribution

Convex optimization
2005
37 引文 (Scopus)

Placement with symmetry constraints for analog layout design using TCG-S

Lin, J. M., Wu, G. M., Chang, Y. W. & Chuang, J. H., 2005 十二月 1, Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005. p. 1135-1138 4 p. 1466541. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; 卷 2).

研究成果: Conference contribution

Analog circuits
Polynomials
44 引文 (Scopus)
Costs
2004
40 引文 (Scopus)
Costs
Experiments
2003
34 引文 (Scopus)
Networks (circuits)
2 引文 (Scopus)

Graph matching-based algorithms for array-based FPGA segmentation design and routing

Lin, J-M., Pan, S. R. & Chang, Y. W., 2003 一月 1, Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference. Institute of Electrical and Electronics Engineers Inc., p. 851-854 4 p. 1195136. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; 卷 2003-January).

研究成果: Conference contribution

Field programmable gate arrays (FPGA)
Routers
Routing algorithms
Computer aided design
2002
8 引文 (Scopus)
Processing
5 引文 (Scopus)

Arbitrary convex and concave rectilinear module packing using TCG

Lin, J. M., Chen, H. L. & Chang, Y. W., 2002 十二月 1, 於 : Proceedings -Design, Automation and Test in Europe, DATE. p. 69-75 7 p., 998251.

研究成果: Conference article

Processing
Planning
18 引文 (Scopus)

Module placement with boundary constraints using B*-trees

Lin, J. M., Yi, H. E. & Chang, Y. W., 2002 八月 1, 於 : IEE Proceedings: Circuits, Devices and Systems. 149, 4, p. 251-256 6 p.

研究成果: Article

Silicon
Trees (mathematics)
Simulated annealing
Costs

Performance-driven placement for dynamically reconfigurable FPGAs

Wu, G. M., Lin, J-M. & Chang, Y. W., 2002 十月 1, 於 : ACM Transactions on Design Automation of Electronic Systems. 7, 4, p. 628-642 15 p.

研究成果: Article

Field programmable gate arrays (FPGA)
Electric power utilization
Scheduling
36 引文 (Scopus)

TCG-S: Orthogonal coupling of P*-admissible representations for general floorplans

Lin, J. M. & Chang, Y. W., 2002 八月 31, Proceedings of the 39th Annual Design Automation Conference, DAC'02. p. 842-847 6 p. (Proceedings - Design Automation Conference).

研究成果: Conference contribution

Costs
Experiments
2001
6 引文 (Scopus)
Field programmable gate arrays (FPGA)
Electric power utilization
Scheduling
Field programmable gate arrays (FPGA)
Scheduling
Networks (circuits)
27 引文 (Scopus)
Field programmable gate arrays (FPGA)
Scheduling
Networks (circuits)
5 引文 (Scopus)
Field programmable gate arrays (FPGA)
Stochastic models
Polynomials
182 引文 (Scopus)
Costs
1998
6 引文 (Scopus)
Field programmable gate arrays (FPGA)
Polynomials