每年研究計畫
個人檔案
學歷
- 1998 美國加州大學柏克萊分校電機博士
研究專長
- 半導體元件
- 半導體物理
- 元件可靠度
經歷
- 1999~1999 台灣積體電路製造公司主任工程師
- 1999~2003 國立成功大學電機系助理教授
- 2003~2008 國立成功大學電機系副教授
- 2008~ 迄今 國立成功大學電機系教授
- 2011~2014 國立成功大學微電子所所長
指紋 查看啟用 Jone-Fang Chen 的研究主題。這些主題標籤來自此人的作品。共同形成了獨特的指紋。
- 15 類似的檔案
Hot carriers
Engineering & Materials Science
Transistors
Engineering & Materials Science
Degradation
Engineering & Materials Science
metal oxide semiconductors
Physics & Astronomy
Light emitting diodes
Engineering & Materials Science
Electric potential
Engineering & Materials Science
Metals
Engineering & Materials Science
MOSFET devices
Engineering & Materials Science
網絡
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研究成果 1995 2019
Simulation-based study of high-density SRAM voltage scaling enabled by inserted-oxide FinFET technology
Wu, Y. T., Ding, F., Connelly, D., Chiang, M-H., Chen, J-F. & Liu, T. J. K., 2019 四月 1, 於 : IEEE Transactions on Electron Devices. 66, 4, p. 1754-1759 6 p., 8661752.研究成果: Article
Static random access storage
Oxides
Nanowires
Transistors
Electric potential
Characteristics and reliability of metal-oxide-semiconductor transistors with various depths of plasma-induced Si recess structure
Chen, J-F., Tsai, Y. L., Chen, C. Y., Hsu, H. T., Kao, C. Y. & Hwang, H. P., 2018 四月 1, 於 : Japanese Journal of Applied Physics. 57, 4, 04FD01.研究成果: Article
recesses
Hot carriers
metal oxide semiconductors
Transistors
transistors
2
引文
(Scopus)
High-density SRAM voltage scaling enabled by inserted-oxide FinFET technology
Wu, Y. T., Chiang, M-H., Chen, J-F., Ding, F., Connelly, D. & Liu, T. J. K., 2018 三月 7, 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017. Institute of Electrical and Electronics Engineers Inc., p. 1-3 3 p. (2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017; 卷 2018-March).研究成果: Conference contribution
Static random access storage
Oxides
Electric potential
Threshold voltage
Ion implantation
Investigation of characteristics and hot-carrier reliability of high-voltage MOS transistors with various doping concentrations in the drift region
Tsai, Y. L., Chen, J-F., Shen, S. F., Hsu, H. T., Kao, C. Y., Chang, K. F. & Hwang, H. P., 2018 十一月 13, 於 : Semiconductor Science and Technology. 33, 12, 125019.研究成果: Article
Hot carriers
MOSFET devices
high voltages
transistors
Doping (additives)
9
引文
(Scopus)
Simulation-Based Study of Hybrid Fin/Planar LDMOS Design for FinFET-Based System-on-Chip Technology
Wu, Y. T., Ding, F., Connelly, D., Zheng, P., Chiang, M. H., Chen, J. F. & Liu, T. J. K., 2017 十月, 於 : IEEE Transactions on Electron Devices. 64, 10, p. 4193-4199 7 p., 8010312.研究成果: Article
Field effect transistors
Electric breakdown
Computer aided design
Semiconductor materials
Electric potential
論文
Analysis on Hot Carrier Reliability for High Voltage MOS Device with Different Processes
作者: 俊諺, 陳., 2017 七月 3監督員: Chen, J. (Supervisor)
學生論文: Master's Thesis
Analysis on Reliability for FinFET with Different Processes
作者: 佑軒, 李., 2018 七月 5監督員: Chen, J. (Supervisor)
學生論文: Master's Thesis
Bifacial Sensing Sides SnO2 MEMS Gas Sensor
作者: 梃嘉, 翁., 2017 七月 5監督員: Chen, J. (Supervisor)
學生論文: Master's Thesis
Breakdown Voltage and Reliability Studies of Devices in NAND Flash Memory Periphery Circuitry
作者: 鈞博, 張., 2014 七月 16監督員: Chen, J. (Supervisor)
學生論文: Master's Thesis
Effect of Gradual Junction on Performance and Reliability of High Voltage MOS Transistors
作者: 登仁, 艾., 2015 七月 1監督員: Chen, J. (Supervisor)
學生論文: Master's Thesis